- Sort Score
- Result 10 results
- Languages All
Results 1 - 3 of 3 for SLW (0.02 sec)
-
src/cmd/compile/internal/ssa/_gen/S390X.rules
// Lower bounded shifts first. No need to check shift value. (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y) (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y) (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y) (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y) (Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
MODUD R3, R4, R5 // 7ca41a12 MODUW R3, R4, R5 // 7ca41a16 MODSD R3, R4, R5 // 7ca41e12 MODSW R3, R4, R5 // 7ca41e16 SLW $8, R3, R4 // 5464402e SLW R3, R4, R5 // 7c851830 SLWCC R3, R4 // 7c841831 SLD $16, R3, R4 // 786483e4 SLD R3, R4, R5 // 7c851836
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// Lower bounded shifts first. No need to check shift value. (Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) => (SLW x y) (Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) => (SLD x y) (Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0)