"varsupsetneqq;":           {'\u2ACC', '\uFE00'},
		"vnsub;":                   {'\u2282', '\u20D2'},
		"vnsup;":                   {'\u2283', '\u20D2'},
		"vsubnE;":                  {'\u2ACB', '\uFE00'},
		"vsubne;":                  {'\u228A', '\uFE00'},
		"vsupnE;":                  {'\u2ACC', '\uFE00'},
		"vsupne;":                  {'\u228B', '\uFE00'},
	}

	"∝":                           "\u221d",
	"⊳":                           "\u22b3",
	"𝓋":                            "\U0001d4cb",
	"⫋︀":                          "\u2acb\ufe00",
	"⊊︀":                          "\u228a\ufe00",
	"⫌︀":                          "\u2acc\ufe00",
	"⊋︀":                          "\u228b\ufe00",

  if (input_ty == result_ty) return getInput();
  return {};
}

//===----------------------------------------------------------------------===//
// SubOp
//===----------------------------------------------------------------------===//

OpFoldResult SubOp::fold(FoldAdaptor adaptor) {
  auto operands = adaptor.getOperands();
  // TODO(b/142478136): Handle fused ops.
  if (getFusedActivationFunction() != "NONE") return {};

		v := c.regoff(p.GetFrom3())

		r := int(p.From.Reg)
		o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))

	case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */
		if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
			c.ctxt.Diag("can't synthesize large constant\n%v", p)
		}
		v := c.vregoff(p.GetFrom3())
		o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)

  // above kind, so that the concat hoisting optimization can still apply.
  if (!exceptions.empty()) {
    int identity_val;
    if (isa<AddOp>(first_arg_op) || isa<SubOp>(first_arg_op))
      identity_val = 0;
    else if (isa<MulOp>(first_arg_op) || isa<DivOp>(first_arg_op) ||
             isa<RealDivOp>(first_arg_op))
      identity_val = 1;
    else
      return failure();

		rel.Off = int32(c.pc)
		rel.Siz = 8
		rel.Sym = p.From.Sym
		rel.Add = 0
		rel.Type = objabi.R_ARM64_GOTPCREL

	case 72: /* vaddp/vand/vcmeq/vorr/vadd/veor/vfmla/vfmls/vbit/vbsl/vcmtst/vsub/vbif/vuzip1/vuzip2/vrax1 Vm.<T>, Vn.<T>, Vd.<T> */
		af := int((p.From.Reg >> 5) & 15)
		af3 := int((p.Reg >> 5) & 15)
		at := int((p.To.Reg >> 5) & 15)
		if af != af3 || af != at {

def TFL_SubOp : TFL_Op<"sub", [
    ResultsBroadcastableShape,
    BinaryOpSameElementTypeConstraint,
    TFL_RuntimePredOpTrait<"Operands do not have valid shapes",
      CPred<"TFL::VerifySubOpShapeConstraints(llvm::cast<SubOp>($_op))">>,
    Pure,
    QuantizableResult,
    DeclareOpInterfaceMethods<TFL_ArithmeticCount>]> {
  let summary = "Subtraction operator";

  let description = [{
    Element-wise subtraction operation.