#include "mlir/IR/Value.h"  // from @llvm-project
#include "mlir/Support/LLVM.h"  // from @llvm-project

namespace mlir {

class Operation;

namespace TF {

class AddV2Op;
class SubOp;
class MulOp;
class DivOp;
class RealDivOp;

// Verifies an reduction op's `input` and reduction `dims`.
LogicalResult VerifyReductionInputAndDims(Value input, Value dims,
                                          Location loc);

// element attributes.
static const APFloat& AddSign(const APFloat& v) { return v; }
static APSInt AddSign(const APInt& v) { return APSInt(v); }

template <typename ResultType>
static LogicalResult FoldDivOpInternal(stablehlo::DivOp op,
                                       PatternRewriter& rewriter) {
  auto adaptor = FoldAdaptor::Create(op);
  if (!adaptor.has_value()) {
    return failure();
  }
  auto const_oprs = adaptor.value().OperandData();

    auto quant_to_float =
        rewriter.create<DivOp>(op.getLoc(), float_diff, quant_diff);

    auto float_to_quant =
        rewriter.create<DivOp>(op.getLoc(), quant_diff, float_diff);

    // During quantization, the quantized min/max values may not line up
    // perfectly with the specified min/max. Nudge them into the right range.
    auto min_scaled =
        rewriter.create<DivOp>(op.getLoc(), float_min, quant_to_float);

  };
  auto scalar_sub = [&](Value lhs, Value rhs) {
    return builder.create<TF::SubOp>(loc, int32_scalar_type, lhs, rhs);
  };
  auto scalar_div = [&](Value lhs, Value rhs) {
    return builder.create<TF::DivOp>(loc, int32_scalar_type, lhs, rhs);
  };

  // effective_filter_size = (filter_size - 1) * dilation_rate + 1
  Value stride_value = CreateScalarConstValue<int32_t>(builder, loc, stride);
  Value dilation_rate_value =

}

// Op registrations
TAC_REGISTER_GPU_OP(AbsOp, CreateBasicOpNoCost);
TAC_REGISTER_GPU_OP(AveragePool2DOp, CreateBasicOpNoCost);
TAC_REGISTER_GPU_OP(CosOp, CreateBasicOpNoCost);
TAC_REGISTER_GPU_OP(DivOp, CreateBasicOpNoCost);
TAC_REGISTER_GPU_OP(ExpOp, CreateBasicOpNoCost);
TAC_REGISTER_GPU_OP(HardSwishOp, CreateBasicOpNoCost);
TAC_REGISTER_GPU_OP(LogOp, CreateBasicOpNoCost);

// definition of Elementwise, all i/o shapes and types must be same-rank
// broadcastable and fully static. Consider moving this into attribute later.
bool IsElementwise(Operation *op) {
  if (!(llvm::isa<TFL::AddOp, TFL::MulOp, TFL::DivOp, TFL::SubOp,
                  TFL::MaximumOp, TFL::MinimumOp>(op))) {
    return false;
  }

  auto opr1_type =
      llvm::dyn_cast_or_null<RankedTensorType>(op->getOperand(0).getType());
  auto opr2_type =

  results.add<DivNoNanOrMulNoNanConstantY<TF::DivNoNanOp, TF::DivOp>>(context);
}

//===----------------------------------------------------------------------===//
// DivOp
//===----------------------------------------------------------------------===//

void DivOp::getCanonicalizationPatterns(RewritePatternSet& results,
                                        MLIRContext* context) {

// 2) Is only used by binary op like AddOp, SubOp, MulOp or DivOp.
bool HasOneUseOrUsedByOnlyBinaryOps(Value out_value) {
  if (out_value.hasOneUse()) {
    return true;
  }

  for (auto &use : out_value.getUses()) {
    mlir::Operation *owner = use.getOwner();
    if (!llvm::isa<mlir::TFL::AddOp>(owner) &&
        !llvm::isa<mlir::TFL::SubOp>(owner) &&
        !llvm::isa<mlir::TFL::DivOp>(owner) &&

    TypeID::get<TF::Conv3DBackpropInputV2Op>(),
    TypeID::get<TF::CumprodOp>(),
    TypeID::get<TF::CumsumOp>(),
    TypeID::get<TF::DepthwiseConv2dNativeOp>(),
    TypeID::get<TF::DivOp>(),
    TypeID::get<TF::DynamicStitchOp>(),
    TypeID::get<TF::_EagerConstOp>(),
    TypeID::get<TF::EmptyOp>(),
    TypeID::get<TF::ExpandDimsOp>(),
    TypeID::get<TF::FakeQuantWithMinMaxVarsOp>(),

                     ApplyExplicitBroadcasting<TF::AddV2Op>,
                     ApplyExplicitBroadcasting<TF::MulOp>,
                     ApplyExplicitBroadcasting<TF::DivOp>,
                     ApplyExplicitBroadcasting<TF::RealDivOp>,
                     ApplyExplicitBroadcasting<TF::SubOp>,
                     ApplyExplicitBroadcasting<TF::FloorDivOp>,