(NEG (NEG x)) => x

(CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) => (CSETM [cc] flag)
(CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) => (CSETM [arm64Negate(cc)] flag)
(CSEL [cc] x (MOVDconst [0]) flag) => (CSEL0 [cc] x flag)
(CSEL [cc] (MOVDconst [0]) y flag) => (CSEL0 [arm64Negate(cc)] y flag)
(CSEL [cc] x (ADDconst [1] a) flag) => (CSINC [cc] x a flag)

	// CRC32CX <Wd>, <Wn>, <Xm>
	{0xffe0fc00, 0x9ac05c00, CRC32CX, instArgs{arg_Wd, arg_Wn, arg_Xm}, nil},
	// CSEL <Wd>, <Wn>, <Wm>, <cond>
	{0xffe00c00, 0x1a800000, CSEL, instArgs{arg_Wd, arg_Wn, arg_Wm, arg_cond_AllowALNV_Normal}, nil},
	// CSEL <Xd>, <Xn>, <Xm>, <cond>
	{0xffe00c00, 0x9a800000, CSEL, instArgs{arg_Xd, arg_Xn, arg_Xm, arg_cond_AllowALNV_Normal}, nil},
	// DCPS1 {#<imm>}

			/* operand order: SHB, VRA, VRB, VRT */
			shb := int(c.regoff(&p.From))
			o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
		}

	case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc
		bc := c.vregoff(&p.From)
		if o.a1 == C_CRBIT {
			// CR bit is encoded as a register, not a constant.
			bc = int64(p.From.Reg)
		}

		// rt = To.Reg, ra = p.Reg, rb = p.From3.Reg

when you have to turn into a chrysalis--you will some day, you
know--and then after that into a butterfly, I should think you'll
feel it a little queer, won't you?'

  `Not a bit,' said the Caterpillar.

  `Well, perhaps your feelings may be different,' said Alice;
`all I know is, it would feel very queer to ME.'

  `You!' said the Caterpillar contemptuously.  `Who are YOU?'

when you have to turn into a chrysalis--you will some day, you
know--and then after that into a butterfly, I should think you'll
feel it a little queer, won't you?'

  `Not a bit,' said the Caterpillar.

  `Well, perhaps your feelings may be different,' said Alice;
`all I know is, it would feel very queer to ME.'

  `You!' said the Caterpillar contemptuously.  `Who are YOU?'

{"Name":"CSEL","Bits":"0|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"CSEL <Wd>, <Wn>, <Wm>, <cond>","Code":"","Alias":""},
{"Name":"CSEL","Bits":"1|0|0|1|1|0|1|0|1|0|0|Rm:5|cond:4|0|0|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"CSEL <Xd>, <Xn>, <Xm>, <cond>","Code":"","Alias":""},

func validateWasmPluginMatch(selectors []*extensions.WasmPlugin_TrafficSelector) error {
	if len(selectors) == 0 {
		return nil
	}
	for selIdx, sel := range selectors {
		if sel == nil {
			return fmt.Errorf("spec.Match[%d] is nil", selIdx)
		}
		for portIdx, port := range sel.Ports {
			if port == nil {
				return fmt.Errorf("spec.Match[%d].Ports[%d] is nil", selIdx, portIdx)
			}

		if p.To.Type == obj.TYPE_NONE {
			rt = REGZERO
		}
		if r == obj.REG_NONE {
			r = REGZERO
		}
		o1 |= (uint32(rf&31) << 16) | (uint32(r&31) << 5) | uint32(rt&31)

	case 18: /* csel cond,Rn,Rm,Rd; cinc/cinv/cneg cond,Rn,Rd; cset cond,Rd */
		o1 = c.oprrr(p, p.As)

		cond := SpecialOperand(p.From.Offset)

         * a key that appears once in `right` might appear multiple times in `left`). We don't
         * guarantee behavior in that case, anyway, and the current behavior is likely undesirable.
         * So that's either a reason to feel free to change it or a reason to not bother thinking
         * further about this.
         */
        V rightValue = uncheckedCastNullableTToT(onlyOnRight.remove(leftKey));

         * a key that appears once in `right` might appear multiple times in `left`). We don't
         * guarantee behavior in that case, anyway, and the current behavior is likely undesirable.
         * So that's either a reason to feel free to change it or a reason to not bother thinking
         * further about this.
         */
        V rightValue = uncheckedCastNullableTToT(onlyOnRight.remove(leftKey));