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Results 1 - 10 of 18 for vsraw (0.05 sec)
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src/cmd/internal/obj/x86/anames.go
"PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFL", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLL", "PSLLO", "PSLLQ", "PSLLW", "PSRAL", "PSRAW", "PSRLL", "PSRLO", "PSRLQ", "PSRLW", "PSUBB", "PSUBL", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", "PTEST", "PUNPCKHBW", "PUNPCKHLQ",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 19.1K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
ANEGV ANOR ANORCC AOR AORCC AORN AORNCC AORIS AREM AREMU ARFI ARLWMI ARLWMICC ARLWNM ARLWNMCC ACLRLSLWI ASLW ASLWCC ASRW ASRAW ASRAWCC ASRWCC ASTBCCC ASTHCCC ASTSW ASTWCCC ASUB ASUBCC ASUBVCC ASUBC ASUBCCC ASUBCV ASUBCVCC ASUBME ASUBMECC ASUBMEVCC ASUBMEV ASUBV
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/net/http/requestwrite_test.go
t.Errorf("writing #%d, err = %q, want %q", i, g, e) continue } if err != nil { continue } if tt.WantWrite != "" { sraw := braw.String() if sraw != tt.WantWrite { t.Errorf("Test %d, expecting:\n%s\nGot:\n%s\n", i, tt.WantWrite, sraw) continue } } if tt.WantProxy != "" { setBody() var praw strings.Builder err = tt.Req.WriteProxy(&praw)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Sep 07 01:07:32 UTC 2022 - 23.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
build-logic/kotlin-dsl-shared-runtime/src/main/kotlin/org/gradle/kotlin/dsl/internal/sharedruntime/codegen/ApiExtensionsGenerator.kt
listOf(targetType.sourceName, name) + parameters.flatMap { apiTypeKey(it.type) } } private fun apiTypeKey(usage: ApiTypeUsage): List<Any> = usage.run { listOf(sourceName, isNullable, isRaw, variance) + typeArguments.flatMap(::apiTypeKey) + bounds.flatMap(::apiTypeKey) } // TODO Policy for extensions with reified generics // // Goals // - make the dsl predictable
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Dec 20 21:41:53 UTC 2023 - 18.1K bytes - Viewed (0) -
test/codegen/shift.go
return v >> (s & 31) } func rshMask32x64(v int32, s uint64) int32 { // arm64:"ASR",-"AND" // ppc64x:"ISEL",-"ORN" // riscv64:"SRAW","OR","SLTIU" // s390x:-"RISBGZ",-"AND",-"LOCGR" return v >> (s & 63) } func rsh5Mask32x64(v int32, s uint64) int32 { // riscv64:"SRAW",-"OR",-"SLTIU" return v >> (s & 31) } func lshMask64x32(v int64, s uint32) int64 { // arm64:"LSL",-"AND"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
SLD $4, R3, R6 // eb630004000d SLD R2, R3, R6 // eb632000000d SRAD $4, R5, R8 // eb850004000a SRAD R3, R5, R8 // eb853000000a SRAW $4, R5, R8 // eb85000400dc SRAW R3, R5, R8 // eb85300000dc RLL R1, R2, R3 // eb321000001d RLL $4, R2, R3 // eb320004001d RLLG R1, R2, R3 // eb321000001c
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
VRLQMI V1, V2, V3 // 10611045 VRLQNM V1, V2, V3 // 10611145 VSLDBI V1, V2, $3, V3 // 106110d6 VSLQ V1, V2, V3 // 10611105 VSRAQ V1, V2, V3 // 10611305 VSRDBI V1, V2, $3, V4 // 108112d6 VSRQ V1, V2, V3 // 10611205 VSTRIBL V1, V2 // 1040080d
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 14.3K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/a.out.go
ALOCGR // find leftmost one AFLOGR // population count APOPCNT // integer bitwise AAND AANDW AOR AORW AXOR AXORW ASLW ASLD ASRW ASRAW ASRD ASRAD ARLL ARLLG ARNSBG ARXSBG AROSBG ARNSBGT ARXSBGT AROSBGT ARISBG ARISBGN ARISBGZ ARISBGNZ ARISBHG ARISBLG ARISBHGZ ARISBLGZ
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC: return true case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC: return true case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC: return true } return false } // revCondMap maps a conditional register bit to its inverse, if possible. var revCondMap = map[string]string{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0)