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Results 1 - 6 of 6 for mtvsrwa (0.13 sec)
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src/cmd/internal/obj/ppc64/a.out.go
ASTXVX ALXSDX ASTXSDX ALXSIWAX ALXSIWZX ASTXSIWX AMFVSRD AMFFPRD AMFVRD AMFVSRWZ AMFVSRLD AMTVSRD AMTFPRD AMTVRD AMTVSRWA AMTVSRWZ AMTVSRDD AMTVSRWS AXXLAND AXXLANDC AXXLEQV AXXLNAND AXXLOR AXXLORC AXXLNOR AXXLORQ AXXLXOR AXXSEL AXXMRGHW AXXMRGLW AXXSPLTW AXXSPLTIB
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9_gtables.go
"STXVRWX", "STXVRHX", "STXVRDX", "STXVRBX", "STXVPX", "STXVP", "SETNBCR", "SETNBC", "SETBCR", "SETBC", "PEXTD", "PDEPD", "MTVSRWM", "MTVSRQM", "MTVSRHM", "MTVSRDM", "MTVSRBMI", "MTVSRBM", "LXVRWX", "LXVRHX", "LXVRDX", "LXVRBX", "LXVPX", "LXVP", "LXVKQ", "DCTFIXQQ", "DCFFIXQQ", "CNTTZDM", "CNTLZDM", "CFUGED",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 16 20:18:50 UTC 2022 - 42.6K bytes - Viewed (0) -
src/internal/bytealg/index_ppc64x.s
// Set up masks for use with VSEL MOVD $0xff, R21 // Set up mask 0xff000000ff000000... SLD $24, R21 MTVSRWS R21, V29 VSLDOI $2, V29, V29, V30 // Mask 0x0000ff000000ff00... MOVD $0xffff, R21 SLD $16, R21 MTVSRWS R21, V31 VSPLTW $0, V0, V1 // Splat 1st word of separator index4loop: LXVB16X (R7)(R0), V2 // Load 16 bytes @R7 into V2 next4:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 31.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
LXVRWX (R1)(R2), VS4 // 7c82089a MTVSRBM R1, V1 // 10300e42 MTVSRBMI $5, V1 // 10220015 MTVSRDM R1, V1 // 10330e42 MTVSRHM R1, V1 // 10310e42 MTVSRQM R1, V1 // 10340e42 MTVSRWM R1, V1 // 10320e42
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 14.3K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
CMP R8, R4 BGE loopexit // Already at end? // vectorize if len(z) is >=3, else jump to scalar loop CMP R4, $3 BLT scalar MTVSRD R9, VS38 // s VSPLTB $7, V6, V4 MTVSRD R5, VS39 // ŝ VSPLTB $7, V7, V2 ADD $-2, R4, R16 PCALIGN $16 loopback: ADD $-1, R8, R10 SLD $3, R10 LXVD2X (R6)(R10), VS32 // load x[i-1], x[i]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"}, // move 64 bits of F register into G register {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0&arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0)