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Results 1 - 10 of 38 for divr (0.07 sec)

  1. test/codegen/arithmetic.go

    		d += e
    	}
    	return d, e
    }
    
    func NoFix32A(divr int32) (int32, int32) {
    	var d int32 = 42
    	var e int32 = 84
    	if divr > 5 {
    		// amd64:-"JMP"
    		// 386:-"JMP"
    		d /= divr
    		// amd64:-"JMP"
    		// 386:-"JMP"
    		e %= divr
    		d += e
    	}
    	return d, e
    }
    
    func NoFix32B(divd int32) (int32, int32) {
    	var d int32
    	var e int32
    	var divr int32 = -1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/x86/anames.go

    	"CVTTSD2SL",
    	"CVTTSD2SQ",
    	"CVTTSS2SL",
    	"CVTTSS2SQ",
    	"CWD",
    	"CWDE",
    	"DAA",
    	"DAS",
    	"DECB",
    	"DECL",
    	"DECQ",
    	"DECW",
    	"DIVB",
    	"DIVL",
    	"DIVPD",
    	"DIVPS",
    	"DIVQ",
    	"DIVSD",
    	"DIVSS",
    	"DIVW",
    	"DPPD",
    	"DPPS",
    	"EMMS",
    	"ENTER",
    	"EXTRACTPS",
    	"F2XM1",
    	"FABS",
    	"FADDD",
    	"FADDDP",
    	"FADDF",
    	"FADDL",
    	"FADDW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 19.1K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Div(32|64)F ...) => (DIV(F|D) ...)
    
    (Mod64 x y) => (Select0 (DIVV x y))
    (Mod64u x y) => (Select0 (DIVVU x y))
    (Mod32 x y) => (Select0 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
    (Mod32u x y) => (Select0 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
    (Mod16 x y) => (Select0 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
    (Mod16u x y) => (Select0 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (Mul32uhilo ...) => (MULTU ...)
    
    (Div32 x y) => (Select1 (DIV x y))
    (Div32u x y) => (Select1 (DIVU x y))
    (Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
    (Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
    (Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))
    (Div8u x y) => (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
    (Div(32|64)F ...) => (DIV(F|D) ...)
    
    (Mod32 x y) => (Select0 (DIV x y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Mul(64|32)F ...) => (FMUL(D|S) ...)
    
    (Div(64|32)F ...) => (FDIV(D|S) ...)
    
    (Div64 x y [false])  => (DIV x y)
    (Div64u ...) => (DIVU ...)
    (Div32 x y [false])  => (DIVW x y)
    (Div32u ...) => (DIVUW ...)
    (Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
    (Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
    (Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  9. src/math/big/natconv.go

    //
    // The iterative method processes n Words by n divW() calls, each of which visits every Word in the
    // incrementally shortened q for a total of n + (n-1) + (n-2) ... + 2 + 1, or n(n+1)/2 divW()'s.
    // Recursive conversion divides q by its approximate square root, yielding two parts, each half
    // the size of q. Using the iterative method on both halves means 2 * (n/2)(n/2 + 1)/2 divW()'s
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Nov 18 17:59:44 UTC 2022
    - 14.6K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/lite/stablehlo/transforms/legalize_hlo_patterns.td

                  (MHLO_AddOp
                    (MHLO_DivOp:$div
                      (MHLO_SubtractOp $arg0, $rem2),
                      $arg1b),
                    (MHLO_ConstantOp $cst_neg1)),
                  $div1)),
              (TF_FloorDivOp $arg0, $arg1),
              [(ValueEquals<"0.0"> $cst),
               (ValueEquals<"-1.0"> $cst_neg1),
               (SameValue $div, $div1),
               (SameValue $rem, $rem1),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Feb 03 08:58:22 UTC 2024
    - 34K bytes
    - Viewed (0)
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