//TODO STTRH 9(R10), R19                   // 53990078
	STXP (R1, R2), (R3), R10                   // 61082ac8
	STXP (R1, R2), (RSP), R10                  // e10b2ac8
	STXPW (R1, R2), (R3), R10                  // 61082a88
	STXPW (R1, R2), (RSP), R10                 // e10b2a88
	STXRW R2, (R19), R20                       // 627e1488
	STXR R15, (R21), R13                       // af7e0dc8

	BFX	$-2, $4, R2, R3    // ERROR "wrong width or LSB"
	BFXU	$4, R2, R5, R2     // ERROR "missing or wrong LSB"
	BFXU	$4, R2, R5         // ERROR "missing or wrong LSB"
	BFC	$12, $8, R2, R3    // ERROR "illegal combination"
	MOVB	R0>>8, R2          // ERROR "illegal shift"
	MOVH	R0<<16, R2         // ERROR "illegal shift"
	MOVBS	R0->8, R2          // ERROR "illegal shift"
	MOVHS	R0<<24, R2         // ERROR "illegal shift"

	MOVW	R1, 4095(R2)(R3)       // 50132fff
	MOVW	R1, 4096(R2)(R3)       // e31320000150
	MOVWZ	R1, 4095(R2)(R3)       // 50132fff
	MOVWZ	R1, 4096(R2)(R3)       // e31320000150
	MOVH	R1, 4095(R2)(R3)       // 40132fff
	MOVHZ   R1, 4095(R2)(R3)       // 40132fff
	MOVH	R1, 4096(R2)(R3)       // e31320000170
	MOVHZ	R1, 4096(R2)(R3)       // e31320000170
	MOVB	R1, 4095(R2)(R3)       // 42132fff

	SETBC CR2EQ, R2                         // 7c4a0300
	SETBCR CR2LT, R2                        // 7c480340
	SETNBC CR2GT, R2                        // 7c490380
	SETNBCR CR6SO, R2                       // 7c5b03c0
	STXVP VS6, 12352(R5)                    // 18c53041
	STXVPX VS22, (R1)(R2)                   // 7ec20b9a
	STXVRBX VS2, (R1)(R2)                   // 7c42091a
	STXVRDX VS2, (R1)(R2)                   // 7c4209da

	JAL	foo(SB) // CALL foo(SB)
	BEQ	R1, 2(PC)
	JMP	foo(SB)
	CALL	foo(SB)
	RET	foo(SB)

	// unary operation
	NEGW	R1, R2 // 00011023
	NEGV	R1, R2 // 0001102f

	WSBH	R1, R2 // 7c0110a0
	DSBH	R1, R2 // 7c0110a4
	DSHD	R1, R2 // 7c011164

	SEB	R1, R2 // 7c011420
	SEH	R1, R2 // 7c011620

	RET

// MSA VMOVI
	VMOVB	$511, W0   // 7b0ff807
	VMOVH	$24, W23   // 7b20c5c7

	CASPD	(R3, R4), (R2), (R8, R9)                         // ERROR "source register pair must start from even register"
	CASPD	(R2, R3), (R2), (R9, R10)                        // ERROR "destination register pair must start from even register"
	CASPD	(R2, R4), (R2), (R8, R9)                         // ERROR "source register pair must be contiguous"

        if (r1 == r2) {
            return true;
        }

        return Objects.equals(r1.getId(), r2.getId())
                && Objects.equals(r1.getUrl(), r2.getUrl())
                && repositoryPolicyEquals(r1.getReleases(), r2.getReleases())
                && repositoryPolicyEquals(r1.getSnapshots(), r2.getSnapshots());
    }

// register parses a full register reference where there is no symbol present (as in 4(R0) or R(10) but not sym(SB))
// including forms involving multiple registers such as R1:R2.
func (p *Parser) register(name string, prefix rune) (r1, r2 int16, scale int8, ok bool) {
	// R1 or R(1) R1:R2 R1,R2 R1+R2, or R1*scale.
	r1, ok = p.registerReference(name)
	if !ok {
		return
	}
	if prefix != 0 && prefix != '*' { // *AX is OK.

        if (r1 == r2) {
            return true;
        }

        return Objects.equals(r1.getId(), r2.getId())
                && Objects.equals(r1.getUrl(), r2.getUrl())
                && policyEquals(r1.getPolicy(false), r2.getPolicy(false))
                && policyEquals(r1.getPolicy(true), r2.getPolicy(true));
    }

	{"R1<<2(R3)", "R1<<2(R3)"},
	{"R(1)<<2(R(3))", "R1<<2(R3)"},
	{"R2", "R2"},
	{"R3", "R3"},
	{"R4", "R4"},
	{"R(4)", "R4"},
	{"R5", "R5"},
	{"R6", "R6"},
	{"R7", "R7"},
	{"R8", "R8"},
	{"[R0,R1,g,R15]", "[R0,R1,g,R15]"},
	{"[R0-R7]", "[R0,R1,R2,R3,R4,R5,R6,R7]"},
	{"[R(0)-R(7)]", "[R0,R1,R2,R3,R4,R5,R6,R7]"},
	{"[R0]", "[R0]"},
	{"[R1-R12]", "[R1,R2,R3,R4,R5,R6,R7,R8,R9,g,R11,R12]"},
	{"armCAS64(SB)", "armCAS64(SB)"},