// ppc64x/power8:"ADDIS\t[$]19,", "ADD\t[$]-10617,"
	out[2] = a + 1234567
	// ppc64x/power10:"ADD\t[$]-1234567,"
	// ppc64x/power9:"ADDIS\t[$]-19,", "ADD\t[$]10617,"
	// ppc64x/power8:"ADDIS\t[$]-19,", "ADD\t[$]10617,"
	out[3] = a - 1234567
	// ppc64x/power10:"ADD\t[$]2147450879,"
	// ppc64x/power9:"ADDIS\t[$]32767,", "ADD\t[$]32767,"
	// ppc64x/power8:"ADDIS\t[$]32767,", "ADD\t[$]32767,"
	out[4] = a + 0x7FFF7FFF

	// arm64:"RBIT","CLZ"
	// s390x:"FLOGR"
	// ppc64x/power8:"ANDN","POPCNTD"
	// ppc64x/power9: "CNTTZD"
	// wasm:"I64Ctz"
	return bits.TrailingZeros(n)
}

func TrailingZeros64(n uint64) int {
	// amd64/v1,amd64/v2:"BSFQ","MOVL\t\\$64","CMOVQEQ"
	// amd64/v3:"TZCNTQ"
	// 386:"BSFL"
	// arm64:"RBIT","CLZ"
	// s390x:"FLOGR"
	// ppc64x/power8:"ANDN","POPCNTD"
	// ppc64x/power9: "CNTTZD"
	// wasm:"I64Ctz"

	CMP   R7, $1
	BNE   power8
	BR    indexbodyp9<>(SB)
#endif
power8:
	BR indexbody<>(SB)

TEXT ·IndexString<ABIInternal>(SB),NOSPLIT|NOFRAME,$0-40
	// R3 = string
	// R4 = length
	// R5 = separator pointer
	// R6 = separator length

#ifdef GOARCH_ppc64le
	MOVBZ internal∕cpu·PPC64+const_offsetPPC64HasPOWER9(SB), R7
	CMP   R7, $1
	BNE   power8
	BR    indexbodyp9<>(SB)

#endif
power8:

	  correspond to the mips64.hardfloat and mips64.softfloat
	  (or mips64le.hardfloat and mips64le.softfloat) feature build tags.
	- For GOARCH=ppc64 or ppc64le,
	  GOPPC64=power8, power9, and power10 correspond to the
	  ppc64.power8, ppc64.power9, and ppc64.power10
	  (or ppc64le.power8, ppc64le.power9, and ppc64le.power10)
	  feature build tags.
	- For GOARCH=riscv64,
	  GORISCV64=rva20u64 and rva22u64 correspond to the riscv64.rva20u64

var PPC64 struct {
	_        CacheLinePad
	HasDARN  bool // Hardware random number generator (requires kernel enablement)
	HasSCV   bool // Syscall vectored (requires kernel enablement)
	IsPOWER8 bool // ISA v2.07 (POWER8)
	IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8
	_        CacheLinePad
}

// S390X contains the supported CPU features of the current IBM Z
// (s390x) platform. If the current platform is not IBM Z then all

		case "power10":
			args = append(args, "-D", "GOPPC64_power10")
			fallthrough
		case "power9":
			args = append(args, "-D", "GOPPC64_power9")
			fallthrough
		default: // This should always be power8.
			args = append(args, "-D", "GOPPC64_power8")
		}
	}

	if cfg.Goarch == "riscv64" {
		// Define GORISCV64_value from cfg.GORISCV64.
		args = append(args, "-D", "GORISCV64_"+cfg.GORISCV64)
	}

#ifdef GOARCH_ppc64le
#  ifdef GOPPC64_power9
#define P8_LXVB16X(RA,RB,VT)  LXVB16X	(RA+RB), VT
#define P8_STXVB16X(VS,RA,RB) STXVB16X	VS, (RA+RB)
#define XXBRD_ON_LE(VA,VT)    XXBRD	VA, VT
#  else
// On POWER8/ppc64le, emulate the POWER9 instructions by loading unaligned
// doublewords and byte-swapping each doubleword to emulate BE load/stores.
#define NEEDS_ESPERM
#define P8_LXVB16X(RA,RB,VT) \
	LXVD2X	(RA+RB), VT \

#define VH4    VS62
#define VH4H   VS63

#define VIN0   VIN

#define ESPERM V10
#define TMP2 V11

// The following macros provide appropriate
// implementations for endianness as well as
// ISA specific for power8 and power9.
#ifdef GOARCH_ppc64le
#  ifdef GOPPC64_power9
#define P8_LXVB16X(RA,RB,VT)   LXVB16X (RA)(RB), VT
#define P8_STXVB16X(VS,RA,RB)  STXVB16X VS, (RA)(RB)
#  else
#define NEEDS_ESPERM