lits = append(lits, lit)
				default:
					return nil, errComplex
				}
			}
			ands = append(ands, lits)
		}
		split = append(split, ands)
	}

	// If all the ORs have length 1 (no actual OR'ing going on),
	// push the top-level ANDs to the bottom level, so that we get
	// one // +build line instead of many.
	maxOr := 0
	for _, or := range split {
		if maxOr < len(or) {
			maxOr = len(or)

	TST $7, R2                                 // 5f0840f2
	ANDS R2, R0, ZR                            // 1f0002ea
	ANDS $7, R2, ZR                            // 5f0840f2
	ANDSW $2863311530, R24, ZR                 // 1ff30172
	ANDSW $2863311530, R24, R23                // 17f30172
	ANDS $-140737488289793, R2, R5             // 458051f2
	ANDSW R26->24, R21, R15                    // af629a6a
	ANDS R30@>44, R3, R26                      // 7ab0deea

	LDP	4*16(a_ptr), (acc0, acc1)// iff select[0] == 0, z3 = z1
	LDP	5*16(a_ptr), (acc2, acc3)
	ANDS	$1, hlp1, ZR
	CSEL	EQ, acc0, y0, y0
	CSEL	EQ, acc1, y1, y1
	CSEL	EQ, acc2, y2, y2
	CSEL	EQ, acc3, y3, y3
	LDP	p256one<>+0x00(SB), (acc0, acc1)
	LDP	p256one<>+0x10(SB), (acc2, acc3)
	ANDS	$2, hlp1, ZR            // iff select[1] == 0, z3 = 1
	CSEL	EQ, acc0, y0, y0
	CSEL	EQ, acc1, y1, y1

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

TEXT errors(SB),$0
	AND	$1, RSP                                          // ERROR "illegal source register"
	ANDS	$1, R0, RSP                                      // ERROR "illegal combination"
	ADDSW	R7->32, R14, R13                                 // ERROR "shift amount out of range 0 to 31"

		d = divd / divr
		// amd64:-"JMP"
		// 386:-"JMP"
		e = divd % divr
		d += e
	}
	return d, e
}

// Check that len() and cap() calls divided by powers of two are
// optimized into shifts and ands

func LenDiv1(a []int) int {
	// 386:"SHRL\t[$]10"
	// amd64:"SHRQ\t[$]10"
	// arm64:"LSR\t[$]10",-"SDIV"
	// arm:"SRL\t[$]10",-".*udiv"
	// ppc64x:"SRD"\t[$]10"
	return len(a) / 1024
}

    assertEqualHashCode(Predicates.and(p1, p2), Predicates.and(p1, p2));

    assertEqualHashCode(Predicates.or(p1, p2), Predicates.or(p1, p2));

    // While not a contractual requirement, we'd like the hash codes for ands
    // & ors of the same predicates to not collide.
    assertTrue(Predicates.and(p1, p2).hashCode() != Predicates.or(p1, p2).hashCode());
  }

  @J2ktIncompatible
  @GwtIncompatible // reflection

    assertEqualHashCode(Predicates.and(p1, p2), Predicates.and(p1, p2));

    assertEqualHashCode(Predicates.or(p1, p2), Predicates.or(p1, p2));

    // While not a contractual requirement, we'd like the hash codes for ands
    // & ors of the same predicates to not collide.
    assertTrue(Predicates.and(p1, p2).hashCode() != Predicates.or(p1, p2).hashCode());
  }

  @J2ktIncompatible
  @GwtIncompatible // reflection

	var op int16
	switch p.next().ScanToken {
	case lex.LSH:
		op = 0
	case lex.RSH:
		op = 1
	case lex.ARR:
		op = 2
	case lex.ROT:
		// following instructions on ARM64 support rotate right
		// AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN
		op = 3
	}
	tok := p.next()
	str := tok.String()
	var count int16
	switch tok.ScanToken {
	case scanner.Ident:
		if p.arch.Family == sys.ARM64 {

(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem)

// fold extensions and ANDs together
(MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
(MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x)
(MOVBreg (ANDconst [c] x)) && c & 0x80   == 0 => (ANDconst [c&0x7f] x)