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Results 1 - 6 of 6 for LXVD2X (0.08 sec)
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src/crypto/aes/asm_ppc64x.s
MOVD $128, R20 \ MOVD $144, R21 \ LXVD2X (R0+Rkeyp), V6 \ ADD $16, Rkeyp \ BEQ CR1, L_start10 \ BEQ CR2, L_start12 \ LXVD2X (R0+Rkeyp), V7 \ LXVD2X (R12+Rkeyp), V8 \ ADD $32, Rkeyp \ L_start12: \ LXVD2X (R0+Rkeyp), V9 \ LXVD2X (R12+Rkeyp), V10 \ ADD $32, Rkeyp \ L_start10: \ LXVD2X (R0+Rkeyp), V11 \ LXVD2X (R12+Rkeyp), V12 \ LXVD2X (R14+Rkeyp), V13 \ LXVD2X (R15+Rkeyp), V14 \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 18:05:32 UTC 2024 - 18.6K bytes - Viewed (0) -
src/crypto/aes/gcm_ppc64x.s
MOVD $48, R18; \ MOVD $64, R19; \ LXVD2X (blk_key)(R0), VS0; \ LXVD2X (blk_key)(R16), VS1; \ LXVD2X (blk_key)(R17), VS2; \ LXVD2X (blk_key)(R18), VS3; \ LXVD2X (blk_key)(R19), VS4; \ ADD $64, R16; \ ADD $64, R17; \ ADD $64, R18; \ ADD $64, R19; \ LXVD2X (blk_key)(R16), VS5; \ LXVD2X (blk_key)(R17), VS6; \ LXVD2X (blk_key)(R18), VS7; \ LXVD2X (blk_key)(R19), VS8; \ ADD $64, R16; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 27.1K bytes - Viewed (0) -
src/crypto/sha512/sha512block_ppc64x.s
MOVWZ $8, TEMP LVSL (TEMP)(R0), LEMASK VSPLTISB $0x0F, KI VXOR KI, LEMASK, LEMASK #endif LXVD2X (CTX)(R_x000), VS32 // v0 = vs32 LXVD2X (CTX)(R_x010), VS34 // v2 = vs34 LXVD2X (CTX)(R_x020), VS36 // v4 = vs36 // unpack the input values into vector registers VSLDOI $8, V0, V0, V1 LXVD2X (CTX)(R_x030), VS38 // v6 = vs38 VSLDOI $8, V2, V2, V3 VSLDOI $8, V4, V4, V5 VSLDOI $8, V6, V6, V7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 15.8K bytes - Viewed (0) -
src/crypto/sha256/sha256block_ppc64x.s
MOVD $0x0c0, R_x0c0 MOVD $0x0d0, R_x0d0 MOVD $0x0e0, R_x0e0 MOVD $0x0f0, R_x0f0 MOVD $0x100, R_x100 MOVD $0x110, R_x110 loop: MOVD TBL_STRT, TBL LVX (TBL)(R_x000), KI LXVD2X (INP)(R_x000), V8 // load v8 in advance // Offload to VSR24-31 (aka FPR24-31) XXLOR V0, V0, VS24 XXLOR V1, V1, VS25 XXLOR V2, V2, VS26 XXLOR V3, V3, VS27 XXLOR V4, V4, VS28 XXLOR V5, V5, VS29
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 14.4K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
VSPLTB $7, V6, V4 MTVSRD R5, VS39 // ŝ VSPLTB $7, V7, V2 ADD $-2, R4, R16 PCALIGN $16 loopback: ADD $-1, R8, R10 SLD $3, R10 LXVD2X (R6)(R10), VS32 // load x[i-1], x[i] SLD $3, R8, R12 LXVD2X (R6)(R12), VS33 // load x[i], x[i+1] VSRD V0, V4, V3 // x[i-1]>>s, x[i]>>s VSLD V1, V2, V5 // x[i]<<ŝ, x[i+1]<<ŝ
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
unsafePoint: true, }, // R31 is temp register // Loop code: // MOVD len/32,R31 set up loop ctr // MOVD R31,CTR // MOVD $16,R31 index register // loop: // LXVD2X (R0)(R4),VS32 // LXVD2X (R31)(R4),VS33 // ADD R4,$32 increment src // STXVD2X VS32,(R0)(R3) // STXVD2X VS33,(R31)(R3) // ADD R3,$32 increment dst // BC 16,0,loop branch ctr
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0)