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Results 1 - 6 of 6 for ROL (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64.s

    	SEXTH	X17, X18				// 13995860
    	XNOR	X18, X19, X20				// 33ca2941
    	XNOR	X18, X19				// b3c92941
    	ZEXTH	X19, X20				// 3bca0908
    
    	// 1.3: Bitwise Rotation (Zbb)
    	ROL	X8, X9, X10				// 33958460 or b30f8040b3dff4013395840033e5af00
    	ROL	X8, X9					// b3948460 or b30f8040b3dff401b3948400b3e49f00
    	ROLW	X9, X10, X11				// bb159560 or b30f9040bb5ff501bb159500b3e5bf00
    	ROLW	X9, X10					// 3b159560 or b30f9040bb5ff5013b15950033e5af00
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (RotateLeft16 <t> x y) => (OR (SLL  <t> x (ANDI [15] <y.Type> y)) (SRL <t> (ZeroExt16to64 x) (ANDI [15] <y.Type> (NEG <y.Type> y))))
    (RotateLeft32 ...) => (ROLW ...)
    (RotateLeft64 ...) => (ROL  ...)
    
    (Less64  ...) => (SLT  ...)
    (Less32  x y) => (SLT  (SignExt32to64 x) (SignExt32to64 y))
    (Less16  x y) => (SLT  (SignExt16to64 x) (SignExt16to64 y))
    (Less8   x y) => (SLT  (SignExt8to64  x) (SignExt8to64  y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true},   // arg0 | arg1
    		{name: "ORI", argLength: 1, reg: gp11, asm: "ORI", aux: "Int64"},      // arg0 | auxint
    		{name: "ROL", argLength: 2, reg: gp21, asm: "ROL"},                    // rotate left arg0 by (arg1 & 63)
    		{name: "ROLW", argLength: 2, reg: gp21, asm: "ROLW"},                  // rotate left least significant word of arg0 by (arg1 & 31), sign extended
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  4. src/crypto/sha1/sha1block_amd64.s

    	VMOVDQU Y0, (OFFSET)(R14)
    
    // Message scheduling pre-compute for rounds 32-79
    // In SHA-1 specification we have:
    // w[i] = (w[i-3] ^ w[i-8]  ^ w[i-14] ^ w[i-16]) rol 1
    // Which is the same as:
    // w[i] = (w[i-6] ^ w[i-16] ^ w[i-28] ^ w[i-32]) rol 2
    // This allows for more efficient vectorization,
    // since w[i]->w[i-3] dependency is broken
    #define PRECALC_32_79(REG,REG_SUB_4,REG_SUB_8,REG_SUB_16,REG_SUB_28,K_OFFSET,OFFSET) \
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 31.5K bytes
    - Viewed (0)
  5. docs/hu/docs/index.md

        return {"item_id": item_id, "q": q}
    ```
    
    **Megjegyzés**:
    
    Ha nem tudod, tekintsd meg a _"Sietsz?"_ szekciót <a href="https://fastapi.tiangolo.com/async/#in-a-hurry" target="_blank">`async` és `await`-ről dokumentációba</a>.
    
    </details>
    
    ### Futtasd le
    
    Indítsd el a szervert a következő paranccsal:
    
    <div class="termy">
    
    ```console
    $ uvicorn main:app --reload
    
    Registered: Mon Jun 17 08:32:26 UTC 2024
    - Last Modified: Mon Apr 29 05:18:04 UTC 2024
    - 20.2K bytes
    - Viewed (0)
  6. src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go

    SuffixLoop:
    	for i, a := range inst.Args {
    		if a == nil {
    			break
    		}
    		switch a := a.(type) {
    		case Reg:
    			switch inst.Op {
    			case MOVSX, MOVZX:
    				continue
    
    			case SHL, SHR, RCL, RCR, ROL, ROR, SAR:
    				if i == 1 {
    					// shift count does not tell us operand size
    					continue
    				}
    
    			case CRC32:
    				// The source argument does tell us operand size,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 21.4K bytes
    - Viewed (0)
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