ADDU	R13, R14, R19	// 01cd9821
	ADDV	R5, R9, R10	// 0125502c
	ADDVU	R13, R14, R19	// 01cd982d

//	LADDW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	ADD	$15176, R14, R9	// 21c93b48
	ADD	$-9, R5, R8	// 20a8fff7
	ADDU	$10, R9, R9	// 2529000a
	ADDV	$15176, R14, R9	// 61c93b48
	ADDV	$-9, R5, R8	// 60a8fff7
	ADDVU	$10, R9, R9	// 6529000a

//	LADDW rreg ',' rreg
//	{

		readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
	)
	ops := []opData{
		// binary ops
		{name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true},   // arg0 + arg1
		{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"}, // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.
		{name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"},                      // arg0 - arg1

		readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
	)
	ops := []opData{
		// binary ops
		{name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true},                             // arg0 + arg1
		{name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"},                           // arg0 + auxInt. auxInt is 32-bit, also in other *const ops.

	MOVV	16(R29), R1
	MOVV	R1, m_vdsoSP(R17)
	MOVV	8(R29), R1
	MOVV	R1, m_vdsoPC(R17)

	// sec is in R3, nsec in R5
	// return nsec in R3
	MOVV	$1000000000, R4
	MULVU	R4, R3
	MOVV	LO, R3
	ADDVU	R5, R3
	MOVV	R3, ret+0(FP)
	RET

fallback:
	MOVV	$SYS_clock_gettime, R2
	SYSCALL
	JMP	finish

TEXT runtime·rtsigprocmask(SB),NOSPLIT|NOFRAME,$0-28
	MOVW	how+0(FP), R4
	MOVV	new+8(FP), R5

	MOVV	16(R3), R25
	MOVV	R25, m_vdsoSP(R24)
	MOVV	8(R3), R25
	MOVV	R25, m_vdsoPC(R24)

	// sec is in R7, nsec in R5
	// return nsec in R7
	MOVV	$1000000000, R4
	MULVU	R4, R7, R7
	ADDVU	R5, R7
	MOVV	R7, ret+0(FP)
	RET

fallback:
	MOVV	$SYS_clock_gettime, R11
	SYSCALL
	JMP	finish

// func rtsigprocmask(how int32, new, old *sigset, size int32)