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Results 1 - 10 of 34 for andc (0.04 sec)
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test/codegen/mathbits.go
// s390x:"ADDE","ADDC\t[$]-1," // mips64:"ADDV","SGTU" // riscv64: "ADD","SLTU" return bits.Add(x, 7, ci) } func AddZ(x, y uint) (r, co uint) { // arm64:"ADDS","ADC",-"ADCS",-"ADD\t",-"CMP" // amd64:"ADDQ","SBBQ","NEGQ",-"NEGL",-"ADCQ" // loong64: "ADDV", "SGTU" // ppc64x: "ADDC", -"ADDE", "ADDZE" // s390x:"ADDC",-"ADDC\t[$]-1," // mips64:"ADDV","SGTU" // riscv64: "ADD","SLTU"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:51:17 UTC 2024 - 19.6K bytes - Viewed (0) -
test/codegen/comparisons.go
func CmpToZero(a, b, d int32, e, f int64, deOptC0, deOptC1 bool) int32 { // arm:`TST`,-`AND` // arm64:`TSTW`,-`AND` // 386:`TESTL`,-`ANDL` // amd64:`TESTL`,-`ANDL` c0 := a&b < 0 // arm:`CMN`,-`ADD` // arm64:`CMNW`,-`ADD` c1 := a+b < 0 // arm:`TEQ`,-`XOR` c2 := a^b < 0 // arm64:`TST`,-`AND` // amd64:`TESTQ`,-`ANDQ` c3 := e&f < 0 // arm64:`CMN`,-`ADD` c4 := e+f < 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 19 16:31:02 UTC 2024 - 15.2K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
MULHDU R5, R14, R11 // high x[i]*y ADDC R15, R10 ADDZE R11 ADDC R9, R10 ADDZE R11, R9 MULLD R5, R16, R14 // low x[i+1]*y MULHDU R5, R16, R15 // high x[i+1]*y ADDC R17, R14 ADDZE R15 ADDC R9, R14 ADDZE R15, R9 MULLD R5, R18, R16 // low x[i+2]*y MULHDU R5, R18, R17 // high x[i+2]*y ADDC R19, R16 ADDZE R17 ADDC R9, R16 ADDZE R17, R9
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(MOVBUreg (ANDI [c] x)) && c < 0 => (ANDI [int64(uint8(c))] x) (MOVHUreg (ANDI [c] x)) && c < 0 => (ANDI [int64(uint16(c))] x) (MOVWUreg (ANDI [c] x)) && c < 0 => (AND (MOVDconst [int64(uint32(c))]) x) // Avoid sign/zero extension for consts. (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))]) (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))]) (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/crypto/sha256/sha256block_amd64.s
RORL $2, DI; \ MOVL a, DX; \ ANDL b, BX; \ RORL $13, DX; \ MOVL a, CX; \ ANDL c, CX; \ XORL DX, DI; \ XORL CX, BX; \ MOVL a, DX; \ MOVL b, CX; \ RORL $22, DX; \ ANDL a, CX; \ XORL CX, BX; \ XORL DX, DI; \ ADDL DI, BX // Calculate T1 and T2, then e = d + T1 and a = T1 + T2. // The values for e and a are stored in d and h, ready for rotation.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 47.3K bytes - Viewed (0) -
src/math/big/arith_s390x.s
MOVD R0, c+56(FP) RET // Update position of x(R6) and z(R8) based on the current counter value and perform copying. // With the assumption that x and z will not overlap with each other or x and z will // point to same memory region, we can use a faster version of copy using only MVC here. // In the following implementation, we have three copy loops, each copying a word, 4 words, and
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 20.3K bytes - Viewed (0) -
test/codegen/memops.go
// amd64: `SUBL\t8\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*4\), [A-Z]+[0-9]*` s -= x[i+2] // 386: `IMULL\t12\([A-Z]+\)\([A-Z]+\*4\), [A-Z]+` s *= x[i+3] // 386: `ANDL\t16\([A-Z]+\)\([A-Z]+\*4\), [A-Z]+` // amd64: `ANDL\t16\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*4\), [A-Z]+[0-9]*` s &= x[i+4] // 386: `ORL\t20\([A-Z]+\)\([A-Z]+\*4\), [A-Z]+` // amd64: `ORL\t20\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*4\), [A-Z]+[0-9]*`
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 12.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
POPCNT R3, R4 // b9e10043 AND R1, R2 // b9800021 AND R1, R2, R3 // b9e42031 AND $-2, R1 // a517fffe AND $-65536, R1 // c01bffff0000 AND $1, R1 // c0a100000001b980001a ANDW R1, R2 // 1421 ANDW R1, R2, R3 // b9f42031 ANDW $1, R1 // c01b00000001 ANDW $131071, R1 // a5160001
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/internal/notsha256/sha256block_amd64.s
RORL $2, DI; \ MOVL a, DX; \ ANDL b, BX; \ RORL $13, DX; \ MOVL a, CX; \ ANDL c, CX; \ XORL DX, DI; \ XORL CX, BX; \ MOVL a, DX; \ MOVL b, CX; \ RORL $22, DX; \ ANDL a, CX; \ XORL CX, BX; \ XORL DX, DI; \ ADDL DI, BX // Calculate T1 and T2, then e = d + T1 and a = T1 + T2. // The values for e and a are stored in d and h, ready for rotation.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 14K bytes - Viewed (0)