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Results 1 - 5 of 5 for SRLI (0.05 sec)

  1. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (SRAI <t> [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y)
    
    // Eliminate right shifts that exceed size of unsigned type.
    (SRLI <t> [x] (MOVBUreg y)) && x >=  8 => (MOVDconst <t> [0])
    (SRLI <t> [x] (MOVHUreg y)) && x >= 16 => (MOVDconst <t> [0])
    (SRLI <t> [x] (MOVWUreg y)) && x >= 32 => (MOVDconst <t> [0])
    
    // Fold constant into immediate instructions where possible.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	XORI	$1, X5, X6				// 13c31200
    	XORI	$1, X5					// 93c21200
    	XORI	$2048, X5				// b71f00009b8f0f80b3c2f201
    
    	SLLI	$1, X5, X6				// 13931200
    	SLLI	$1, X5					// 93921200
    	SRLI	$1, X5, X6				// 13d31200
    	SRLI	$1, X5					// 93d21200
    	SRAI	$1, X5, X6				// 13d31240
    	SRAI	$1, X5					// 93d21240
    
    	ADD	X6, X5, X7				// b3836200
    	ADD	X5, X6					// 33035300
    	ADD	$2047, X5, X6				// 1383f27f
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  3. test/codegen/shift.go

    // ------------------ //
    
    func lshConst64x64(v int64) int64 {
    	// ppc64x:"SLD"
    	// riscv64:"SLLI",-"AND",-"SLTIU"
    	return v << uint64(33)
    }
    
    func rshConst64Ux64(v uint64) uint64 {
    	// ppc64x:"SRD"
    	// riscv64:"SRLI\t",-"AND",-"SLTIU"
    	return v >> uint64(33)
    }
    
    func rshConst64Ux64Overflow32(v uint32) uint64 {
    	// riscv64:"MOV\t\\$0,",-"SRL"
    	return uint64(v) >> 32
    }
    
    func rshConst64Ux64Overflow16(v uint16) uint64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "SRAIW", argLength: 1, reg: gp11, asm: "SRAIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, arithmetic right shift of 32 bit value, sign extended to 64 bits
    		{name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, logical right shift
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  5. src/cmd/link/internal/riscv64/asm.go

    	//      l[w|d] t3, %pcrel_lo(1b)(t2)    # _dl_runtime_resolve
    	//      addi   t1, t1, -(hdr size + 12) # shifted .got.plt offset
    	//      addi   t0, t2, %pcrel_lo(1b)    # &.got.plt
    	//      srli   t1, t1, log2(16/PTRSIZE) # .got.plt offset
    	//      l[w|d] t0, PTRSIZE(t0)          # link map
    	//      jr     t3
    
    	plt.AddSymRef(ctxt.Arch, gotplt.Sym(), 0, objabi.R_RISCV_PCREL_HI20, 4)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 01 08:06:08 UTC 2024
    - 22.8K bytes
    - Viewed (0)
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