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Results 1 - 4 of 4 for SLLV (0.02 sec)

  1. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Lsh64x32 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y))) (SLLV <t> x (ZeroExt32to64 y)))
    (Lsh64x16 <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y))) (SLLV <t> x (ZeroExt16to64 y)))
    (Lsh64x8  <t> x y) => (AND (NEGV <t> (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt8to64  y))) (SLLV <t> x (ZeroExt8to64  y)))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Lsh64x64 <t> x y) => (MASKEQZ (SLLV <t> x                y)  (SGTU (MOVVconst <typ.UInt64> [64])                y))
    (Lsh64x32 <t> x y) => (MASKEQZ (SLLV <t> x (ZeroExt32to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt32to64 y)))
    (Lsh64x16 <t> x y) => (MASKEQZ (SLLV <t> x (ZeroExt16to64 y)) (SGTU (MOVVconst <typ.UInt64> [64]) (ZeroExt16to64 y)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/mips64.s

    //	}
    	SLL	R1, R2, R3	// 00221804
    	SLLV	R10, R22, R21	// 0156a814
    	SRL	R27, R6, R17	// 03668806
    	SRLV	R27, R6, R17	// 03668816
    	SRA	R11, R19, R20	// 0173a007
    	SRAV	R20, R19, R19	// 02939817
    	ROTR	R19, R18, R20	// 0272a046
    	ROTRV	R9, R13, R16	// 012d8056
    
    //	LSHW rreg ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SLL	R1, R2		// 00221004
    	SLLV	R10, R22	// 0156b014
    	SRL	R27, R6   	// 03663006
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "MASKNEZ", argLength: 2, reg: gp21, asm: "MASKNEZ"}, // returns 0 if arg1 != 0, otherwise returns arg0
    
    		// shifts
    		{name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"},                      // arg0 << arg1, shift amount is mod 64
    		{name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"},   // arg0 << auxInt
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
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