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src/cmd/asm/internal/asm/testdata/s390x.s
VMNH V1, V2, V30 // e7e1200018fe VERLLVF V2, V30, V27 // e7be20002c73 VSCBIB V0, V23, V24 // e78700000cf5 VN V2, V1, V0 // e70210000068 VNC V2, V1, V0 // e70210000069 VO V2, V1, V0 // e7021000006a VX V2, V1, V0 // e7021000006d VN V16, V1 // e71010000468 VNC V16, V1 // e71010000469
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Nov 22 03:55:32 GMT 2023 - 21.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
UMULL R19, R22, R19 // d37eb39b UXTBW R2, R6 // 461c0053 UXTHW R7, R20 // f43c0053 VCNT V0.B8, V0.B8 // 0058200e VCNT V0.B16, V0.B16 // 0058204e WFE // 5f2003d5 WFI // 7f2003d5
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Viewed (1) -
src/cmd/asm/internal/asm/operand_test.go
{"VS54", "VS54"}, {"VS55", "VS55"}, {"VS56", "VS56"}, {"VS57", "VS57"}, {"VS58", "VS58"}, {"VS59", "VS59"}, {"VS60", "VS60"}, {"VS61", "VS61"}, {"VS62", "VS62"}, {"VS63", "VS63"}, {"V0", "V0"}, {"V1", "V1"}, {"V2", "V2"}, {"V3", "V3"}, {"V4", "V4"}, {"V5", "V5"}, {"V6", "V6"}, {"V7", "V7"}, {"V8", "V8"}, {"V9", "V9"}, {"V10", "V10"}, {"V11", "V11"},
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
register["R18_PLATFORM"] = register["R18"] delete(register, "R18") for i := arm64.REG_F0; i <= arm64.REG_F31; i++ { register[obj.Rconv(i)] = int16(i) } for i := arm64.REG_V0; i <= arm64.REG_V31; i++ { register[obj.Rconv(i)] = int16(i) } // System registers. for i := 0; i < len(arm64.SystemReg); i++ { register[arm64.SystemReg[i].Name] = arm64.SystemReg[i].Reg }
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm64.go
if 0 <= n && n <= 31 { return arm64.REG_F0 + n, true } case "R": if 0 <= n && n <= 30 { // not 31 return arm64.REG_R0 + n, true } case "V": if 0 <= n && n <= 31 { return arm64.REG_V0 + n, true } } return 0, false } // ARM64RegisterShift constructs an ARM64 register with shift operation. func ARM64RegisterShift(reg, op, count int16) (int64, error) {
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src/cmd/asm/internal/asm/parse.go
// registers in []. There may be comma-separated ranges or individual // registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4]. // For ARM, only R0 through R15 may appear. // For ARM64, V0 through V31 with arrangement may appear. // // For 386/AMD64 register list specifies 4VNNIW-style multi-source operand. // For range of 4 elements, Intel manual uses "+3" notation, for example: //
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src/cmd/asm/internal/asm/testdata/arm64error.s
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 37.8K bytes - Viewed (0)