VP4DPWSSD 15(DX)(BX*8), [Z2-Z5], K4, Z17           // 62e26f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z12-Z15], K4, Z17          // 62e21f4c528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z12-Z15], K4, Z17         // 62e21f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z22-Z25], K4, Z17          // 62e24f44528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z22-Z25], K4, Z17         // 62e24f44528cda0f000000

	// CLWB instructions:
	CLWB BX                          // ERROR "invalid instruction"
	// CLDEMOTE instructions:
	CLDEMOTE BX                      // ERROR "invalid instruction"
	// WAITPKG instructions:
	TPAUSE (BX)                      // ERROR "invalid instruction"
	UMONITOR (BX)                    // ERROR "invalid instruction"
	UMWAIT (BX)                      // ERROR "invalid instruction"

	DIVB	foo+4(SB)
	PUSHL	$foo+4(SB)
	POPL		AX

// LTYPE3 rimrem	{ outcode(int($1), &$2); }
	SUBB	$1, AX
	SUBB	$1, foo+4(SB)
	SUBB	BX, AX
	SUBB	BX, foo+4(SB)

// LTYPE4 remrim	{ outcode(int($1), &$2); }
	CMPB	AX, $1
	CMPB	foo+4(SB), $4
	CMPB	BX, AX
	CMPB	foo+4(SB), BX

// LTYPER nonrel	{ outcode(int($1), &$2); }
label:
	JC	label // JCS
	JC	-1(PC) // JCS -1(PC)

// LTYPEC spec3	{ outcode(int($1), &$2); }

	VPCLMULQDQ $97, 15(DX)(BX*8), Z0, Z12              // 62737d4844a4da0f00000061 or 6273fd4844a4da0f00000061
	VPCLMULQDQ $97, Z9, Z26, Z12                       // 62532d4044e161 or 6253ad4044e161
	VPCLMULQDQ $97, Z3, Z26, Z12                       // 62732d4044e361 or 6273ad4044e361
	VPCLMULQDQ $97, 7(SI)(DI*1), Z26, Z12              // 62732d4044a43e0700000061 or 6273ad4044a43e0700000061

	VPOPCNTD -15(BX), K5, Y26                          // 62627d2d5593f1ffffff
	VPOPCNTD Y22, K5, Y30                              // 62227d2d55f6
	VPOPCNTD Y3, K5, Y30                               // 62627d2d55f3
	VPOPCNTD Y15, K5, Y30                              // 62427d2d55f7
	VPOPCNTD -15(R14)(R15*1), K5, Y30                  // 62027d2d55b43ef1ffffff
	VPOPCNTD -15(BX), K5, Y30                          // 62627d2d55b3f1ffffff

			"\tPINSRW	$index, (BP)(R8*4), xmm",
			"#define LOAD(off, reg) \\",
			"\tMOVBLZX	(off*4)(R12),	reg \\",
			"\tADDB	reg,		DX",
			"KEYROUND(X0, LOAD, 8, AX, BX, 0)",
		),
		"\n.MOVBLZX.(.BP.).(.DX.*.4.).,.R8.\n.\n.MOVBLZX.(.(.8.+.1.).*.4.).(.R12.).,.BX.\n.ADDB.BX.,.DX.\n.MOVB.R8.,.(.8.*.4.).(.R12.).\n.PINSRW.$.0.,.(.BP.).(.R8.*.4.).,.X0.\n",
	},
	{
		"taken #ifdef",
		lines(
			"#define A",
			"#ifdef A",

// LTYPEM spec6	{ outcode($1, &$2); }
	MOVL	AX, R11
	MOVL	$4, R11
//	MOVL	AX, 0(AX):DS // no longer works - did it ever?

// LTYPEI spec7	{ outcode($1, &$2); }
	IMULB	DX
	IMULW	DX, BX
	IMULL	R11, R12
	IMULQ	foo+4(SB), R11

// LTYPEXC spec8	{ outcode($1, &$2); }
	CMPPD	X1, X2, 4
	CMPPD	foo+4(SB), X2, 4

// LTYPEX spec9	{ outcode($1, &$2); }
	PINSRW	$4, AX, X2

TEXT ·a14(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ R15, AX, BX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here"
	RET
TEXT ·a15(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ AX, R15, BX
	ADDQ $1, R15
	RET
TEXT ·a16(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	MULXQ AX, BX, R15
	ADDQ $1, R15
	RET
TEXT ·a17(SB), 0, $0-0

	// Included to simplify validation of CL that fixed that.
	MOVQ (AX), M0  // 0f6f00
	MOVQ M0, 8(SP) // 0f7f442408
	MOVQ 8(SP), M0 // 0f6f442408
	MOVQ M0, (AX)  // 0f7f00
	MOVQ M0, (BX)  // 0f7f03
	// On non-64bit arch, Go asm allowed uint32 offsets instead of int32.
	// These tests check that property for backwards-compatibility.
	MOVL 2147483648(AX), AX  // 8b8000000080
	MOVL -2147483648(AX), AX // 8b8000000080

	"DBW": arm.C_WBIT | arm.C_PBIT,
	"DAW": arm.C_WBIT,
	"IB":  arm.C_PBIT | arm.C_UBIT,
	"IA":  arm.C_UBIT,
	"DB":  arm.C_PBIT,
	"DA":  0,
}

var armJump = map[string]bool{
	"B":    true,
	"BL":   true,
	"BX":   true,
	"BEQ":  true,
	"BNE":  true,
	"BCS":  true,
	"BHS":  true,
	"BCC":  true,
	"BLO":  true,
	"BMI":  true,
	"BPL":  true,
	"BVS":  true,
	"BVC":  true,
	"BHI":  true,
	"BLS":  true,