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Results 1 - 10 of 71 for r15 (0.02 sec)

  1. src/runtime/cgo/asm_s390x.s

    	MOVD	R2, 8(R15)	// fn unsafe.Pointer
    	MOVD	R3, 16(R15)	// a unsafe.Pointer
    	// Skip R4 = n uint32
    	MOVD	R5, 24(R15)	// ctxt uintptr
    	BL	runtime·cgocallback(SB)
    
    	FMOVD	32(R15), F8
    	FMOVD	40(R15), F9
    	FMOVD	48(R15), F10
    	FMOVD	56(R15), F11
    	FMOVD	64(R15), F12
    	FMOVD	72(R15), F13
    	FMOVD	80(R15), F14
    	FMOVD	88(R15), F15
    
    	// De-allocate stack frame.
    	MOVD	$96(R15), R15
    
    	// Restore R6-R15.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 00:43:51 UTC 2023
    - 1.7K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s

    	XORQ R15, R15
    	RET
    TEXT ·a5(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	XORL R15, R15
    	RET
    TEXT ·a6(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	POPQ R15
    	PUSHQ R15
    	RET
    TEXT ·a7(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	MOVQ R15, AX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here"
    	RET
    TEXT ·a8(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 15 20:45:41 UTC 2023
    - 4.8K bytes
    - Viewed (0)
  3. src/runtime/cgo/gcc_s390x.S

    	std     %f9, 8(%r15)
    	std     %f10, 16(%r15)
    	std     %f11, 24(%r15)
    	std     %f12, 32(%r15)
    	std     %f13, 40(%r15)
    	std     %f14, 48(%r15)
    	std     %f15, 56(%r15)
    
    	/* restore g pointer */
    	lgr     %r13, %r3
    
    	/* call fn */
    	basr    %r14, %r2
    
    	/* restore floating point registers */
    	ld      %f8, 0(%r15)
    	ld      %f9, 8(%r15)
    	ld      %f10, 16(%r15)
    	ld      %f11, 24(%r15)
    	ld      %f12, 32(%r15)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Dec 05 16:41:48 UTC 2022
    - 1.4K bytes
    - Viewed (0)
  4. src/crypto/subtle/xor_ppc64x.s

    	// Case for 8 ≤ n < 16 bytes
    	MOVD	(R4)(R8), R14   // R14 = a[i,...,i+7]
    	MOVD	(R5)(R8), R15   // R15 = b[i,...,i+7]
    	XOR	R14, R15, R16   // R16 = a[] ^ b[]
    	SUB	$8, R6          // n = n - 8
    	MOVD	R16, (R3)(R8)   // Store to dst
    	ADD	$8, R8
    xor4:
    	CMP	R6, $4
    	BLT	xor2
    	MOVWZ	(R4)(R8), R14
    	MOVWZ	(R5)(R8), R15
    	XOR	R14, R15, R16
    	MOVW	R16, (R3)(R8)
    	ADD	$4,R8
    	ADD	$-4,R6
    xor2:
    	CMP	R6, $2
    	BLT	xor1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  5. src/crypto/internal/edwards25519/field/fe_amd64.s

    	// r4 = a0×b4
    	MOVQ (CX), AX
    	MULQ 32(BX)
    	MOVQ AX, R15
    	MOVQ DX, R14
    
    	// r4 += a1×b3
    	MOVQ 8(CX), AX
    	MULQ 24(BX)
    	ADDQ AX, R15
    	ADCQ DX, R14
    
    	// r4 += a2×b2
    	MOVQ 16(CX), AX
    	MULQ 16(BX)
    	ADDQ AX, R15
    	ADCQ DX, R14
    
    	// r4 += a3×b1
    	MOVQ 24(CX), AX
    	MULQ 8(BX)
    	ADDQ AX, R15
    	ADCQ DX, R14
    
    	// r4 += a4×b0
    	MOVQ 32(CX), AX
    	MULQ (BX)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  6. src/vendor/golang.org/x/crypto/internal/poly1305/sum_amd64.s

    	MOVQ msg_base+8(FP), SI
    	MOVQ msg_len+16(FP), R15
    
    	MOVQ 0(DI), R8   // h0
    	MOVQ 8(DI), R9   // h1
    	MOVQ 16(DI), R10 // h2
    	MOVQ 24(DI), R11 // r0
    	MOVQ 32(DI), R12 // r1
    
    	CMPQ R15, $16
    	JB   bytes_between_0_and_15
    
    loop:
    	POLY1305_ADD(SI, R8, R9, R10)
    
    multiply:
    	POLY1305_MUL(R8, R9, R10, R11, R12, BX, CX, R13, R14)
    	SUBQ $16, R15
    	CMPQ R15, $16
    	JAE  loop
    
    bytes_between_0_and_15:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 2.5K bytes
    - Viewed (0)
  7. src/runtime/memclr_ppc64x.s

    zero512setup16:
    	ANDCC $127, R3, R14 // < 128 byte alignment
    	BEQ   zero512setup  // handle 128 byte alignment
    	MOVD  $128, R15
    	SUB   R14, R15, R14 // find increment to 128 alignment
    	SRD   $4, R14, R15  // number of 16 byte chunks
    	MOVD   R15, CTR         // loop counter of 16 bytes
    	XXLXOR VS32, VS32, VS32 // clear VS32 (V0)
    
    zero512preloop:  // clear up to 128 alignment
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 16 17:08:59 UTC 2023
    - 4.4K bytes
    - Viewed (0)
  8. src/crypto/internal/bigmod/nat_ppc64x.s

    	MOVD	24(R4), R20	// x[i+3]
    	MOVD	0(R3), R15	// z[i]
    	MOVD	8(R3), R17	// z[i+1]
    	MOVD	16(R3), R19	// z[i+2]
    	MOVD	24(R3), R21	// z[i+3]
    	MULLD	R5, R14, R10	// low x[i]*y
    	MULHDU	R5, R14, R11	// high x[i]*y
    	ADDC	R15, R10
    	ADDZE	R11
    	ADDC	R9, R10
    	ADDZE	R11, R9
    	MULLD	R5, R16, R14	// low x[i+1]*y
    	MULHDU	R5, R16, R15	// high x[i+1]*y
    	ADDC	R17, R14
    	ADDZE	R15
    	ADDC	R9, R14
    	ADDZE	R15, R9
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jan 25 19:32:43 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/x86/obj6_test.go

    MOVQ name(SB), AX -> NOP; MOVQ name@GOT(SB), R15; MOVQ (R15), AX
    MOVQ name+10(SB), AX -> NOP; MOVQ name@GOT(SB), R15; MOVQ 10(R15), AX
    
    CMPQ name(SB), $0 -> NOP; MOVQ name@GOT(SB), R15; CMPQ (R15), $0
    
    MOVQ $1, name(SB) -> NOP; MOVQ name@GOT(SB), R15; MOVQ $1, (R15)
    MOVQ $1, name+10(SB) -> NOP; MOVQ name@GOT(SB), R15; MOVQ $1, 10(R15)
    `
    
    type ParsedTestData struct {
    	input              string
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 15 20:21:30 UTC 2022
    - 4.5K bytes
    - Viewed (0)
  10. src/internal/bytealg/equal_ppc64x.s

    	MOVD	$16, R14	// index for VSX loads and stores
    	MOVD	$32, R15
    	MOVD	$48, R16
    	ANDCC	$0x3F, R5, R5	// len%64==0?
    
    	PCALIGN $16
    loop64:
    	LXVD2X	(R8+R0), V0
    	LXVD2X	(R4+R0), V1
    	VCMPEQUBCC V0, V1, V2	// compare, setting CR6
    	BGELR_CR6
    	LXVD2X	(R8+R14), V0
    	LXVD2X	(R4+R14), V1
    	VCMPEQUBCC	V0, V1, V2
    	BGELR_CR6
    	LXVD2X	(R8+R15), V0
    	LXVD2X	(R4+R15), V1
    	VCMPEQUBCC	V0, V1, V2
    	BGELR_CR6
    	LXVD2X	(R8+R16), V0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 16:47:45 UTC 2023
    - 4.9K bytes
    - Viewed (0)
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