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Results 41 - 50 of 70 for fdiv (0.04 sec)
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src/cmd/vendor/golang.org/x/arch/x86/x86asm/plan9x.go
CMP: true, CMPXCHG: true, CVTSI2SD: true, CVTSI2SS: true, CVTSD2SI: true, CVTSS2SI: true, CVTTSD2SI: true, CVTTSS2SI: true, DEC: true, DIV: true, FLDENV: true, FRSTOR: true, IDIV: true, IMUL: true, IN: true, INC: true, LEA: true, MOV: true, MOVNTI: true, MUL: true, NEG: true,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 12 20:38:21 UTC 2023 - 7.2K bytes - Viewed (0) -
src/runtime/vlop_arm.s
// It's not strictly true that there are no local pointers. // It could be that the saved registers Rq, Rr, Rs, and Rm // contain pointers. However, the only way this can matter // is if the stack grows (which it can't, udiv is nosplit) // or if a fault happens and more frames are added to // the stack due to deferred functions. // In the latter case, the stack can grow arbitrarily, // and garbage collection can happen, and those
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jun 04 07:25:06 UTC 2020 - 7.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/a.out.go
AROSBGT ARISBG ARISBGN ARISBGZ ARISBGNZ ARISBHG ARISBLG ARISBHGZ ARISBLGZ // floating point AFABS AFADD AFADDS AFCMPO AFCMPU ACEBR AFDIV AFDIVS AFMADD AFMADDS AFMOVD AFMOVS AFMSUB AFMSUBS AFMUL AFMULS AFNABS AFNEG AFNEGS ALEDBR ALDEBR ALPDFR ALNDFR AFSUB AFSUBS AFSQRT
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/cpu.go
AADDW ASLLW ASRLW ASUBW ASRAW // 5.3: Load and Store Instructions (RV64I) ALD ASD // 7.1: Multiplication Operations AMUL AMULH AMULHU AMULHSU AMULW ADIV ADIVU AREM AREMU ADIVW ADIVUW AREMW AREMUW // 8.2: Load-Reserved/Store-Conditional Instructions ALRD ASCD ALRW ASCW // 8.3: Atomic Memory Operations
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
AEQV AEQVCC AEXTSB AEXTSBCC AEXTSH AEXTSHCC AFABS AFABSCC AFADD AFADDCC AFADDS AFADDSCC AFCMPO AFCMPU AFCTIW AFCTIWCC AFCTIWZ AFCTIWZCC AFDIV AFDIVCC AFDIVS AFDIVSCC AFMADD AFMADDCC AFMADDS AFMADDSCC AFMOVD AFMOVDCC AFMOVDU AFMOVS AFMOVSU AFMOVSX AFMOVSZ AFMSUB AFMSUBCC AFMSUBS
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
FSW F0, 4(X5) // 27a20200 // 11.6: Single-Precision Floating-Point Computational Instructions FADDS F1, F0, F2 // 53011000 FSUBS F1, F0, F2 // 53011008 FMULS F1, F0, F2 // 53011010 FDIVS F1, F0, F2 // 53011018 FMINS F1, F0, F2 // 53011028 FMAXS F1, F0, F2 // 53111028 FSQRTS F0, F1 // d3000058 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x73, 0x1, 0x0, 0, 0x0} case ACSRRWI: return &inst{0x73, 0x5, 0x0, 0, 0x0} case ACTZ: return &inst{0x13, 0x1, 0x1, 1537, 0x30} case ACTZW: return &inst{0x1b, 0x1, 0x1, 1537, 0x30} case ADIV: return &inst{0x33, 0x4, 0x0, 32, 0x1} case ADIVU: return &inst{0x33, 0x5, 0x0, 32, 0x1} case ADIVUW: return &inst{0x3b, 0x5, 0x0, 32, 0x1} case ADIVW: return &inst{0x3b, 0x4, 0x0, 32, 0x1}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssagen/ssa.go
{ir.ODIV, types.TFLOAT32}: ssa.OpDiv32F, {ir.ODIV, types.TFLOAT64}: ssa.OpDiv64F, {ir.ODIV, types.TINT8}: ssa.OpDiv8, {ir.ODIV, types.TUINT8}: ssa.OpDiv8u, {ir.ODIV, types.TINT16}: ssa.OpDiv16, {ir.ODIV, types.TUINT16}: ssa.OpDiv16u, {ir.ODIV, types.TINT32}: ssa.OpDiv32, {ir.ODIV, types.TUINT32}: ssa.OpDiv32u, {ir.ODIV, types.TINT64}: ssa.OpDiv64,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jun 10 19:44:43 UTC 2024 - 284.9K bytes - Viewed (0) -
test/codegen/mathbits.go
// riscv64:"MUL\t",-"MULHU" _, lo := bits.Mul64(x, y) return lo } // --------------- // // bits.Div* // // --------------- // func Div(hi, lo, x uint) (q, r uint) { // amd64:"DIVQ" return bits.Div(hi, lo, x) } func Div32(hi, lo, x uint32) (q, r uint32) { // arm64:"ORR","UDIV","MSUB",-"UREM" return bits.Div32(hi, lo, x) } func Div64(hi, lo, x uint64) (q, r uint64) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:51:17 UTC 2024 - 19.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
{AMOVHU, C_REG, C_NONE, C_REG, 14, 8, 0, 0, 0, 0}, {AMUL, C_REG, C_REG, C_REG, 15, 4, 0, 0, 0, C_SBIT}, {AMUL, C_REG, C_NONE, C_REG, 15, 4, 0, 0, 0, C_SBIT}, {ADIV, C_REG, C_REG, C_REG, 16, 4, 0, 0, 0, 0}, {ADIV, C_REG, C_NONE, C_REG, 16, 4, 0, 0, 0, 0}, {ADIVHW, C_REG, C_REG, C_REG, 105, 4, 0, 0, 0, 0}, {ADIVHW, C_REG, C_NONE, C_REG, 105, 4, 0, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0)