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Results 21 - 30 of 32 for dmulq (0.05 sec)
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src/vendor/golang.org/x/crypto/chacha20poly1305/chacha20poly1305_amd64.s
#define polyMulStage1 MOVQ (0*8)(BP), AX; MOVQ AX, t2; MULQ acc0; MOVQ AX, t0; MOVQ DX, t1; MOVQ (0*8)(BP), AX; MULQ acc1; IMULQ acc2, t2; ADDQ AX, t1; ADCQ DX, t2 #define polyMulStage2 MOVQ (1*8)(BP), AX; MOVQ AX, t3; MULQ acc0; ADDQ AX, t1; ADCQ $0, DX; MOVQ DX, acc0; MOVQ (1*8)(BP), AX; MULQ acc1; ADDQ AX, t2; ADCQ $0, DX #define polyMulStage3 IMULQ acc2, t3; ADDQ acc0, t2; ADCQ DX, t3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 29 21:28:33 UTC 2023 - 105.6K bytes - Viewed (0) -
src/runtime/sys_dragonfly_amd64.s
MOVL $232, AX MOVQ $4, DI // CLOCK_MONOTONIC LEAQ 8(SP), SI SYSCALL MOVQ 8(SP), AX // sec MOVQ 16(SP), DX // nsec // sec is in AX, nsec in DX // return nsec in AX IMULQ $1000000000, AX ADDQ DX, AX MOVQ AX, ret+0(FP) RET TEXT runtime·sigaction(SB),NOSPLIT,$-8 MOVL sig+0(FP), DI // arg 1 sig MOVQ new+8(FP), SI // arg 2 act MOVQ old+16(FP), DX // arg 3 oact
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 8.3K bytes - Viewed (0) -
test/codegen/mathbits.go
// bits.Mul* // // --------------- // func Mul(x, y uint) (hi, lo uint) { // amd64:"MULQ" // arm64:"UMULH","MUL" // ppc64x:"MULHDU","MULLD" // s390x:"MLGR" // mips64: "MULVU" // riscv64:"MULHU","MUL" return bits.Mul(x, y) } func Mul64(x, y uint64) (hi, lo uint64) { // amd64:"MULQ" // arm64:"UMULH","MUL" // ppc64x:"MULHDU","MULLD" // s390x:"MLGR" // mips64: "MULVU"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 18:51:17 UTC 2024 - 19.6K bytes - Viewed (0) -
src/runtime/sys_netbsd_amd64.s
LEAQ 8(SP), SI // arg 2 - tp MOVL $SYS___clock_gettime50, AX SYSCALL MOVQ 8(SP), AX // sec MOVQ 16(SP), DX // nsec // sec is in AX, nsec in DX // return nsec in AX IMULQ $1000000000, AX ADDQ DX, AX MOVQ AX, ret+0(FP) RET TEXT runtime·getcontext(SB),NOSPLIT,$-8 MOVQ ctxt+0(FP), DI // arg 1 - context MOVL $SYS_getcontext, AX SYSCALL JCC 2(PC)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 9.8K bytes - Viewed (0) -
src/cmd/internal/obj/x86/aenum.go
AMOVSQ AMOVSS AMOVSW AMOVSWW AMOVUPD AMOVUPS AMOVW AMOVWLSX AMOVWLZX AMOVWQSX AMOVWQZX AMOVZWW AMPSADBW AMULB AMULL AMULPD AMULPS AMULQ AMULSD AMULSS AMULW AMULXL AMULXQ AMWAIT ANEGB ANEGL ANEGQ ANEGW ANOPL ANOPW ANOTB ANOTL ANOTQ ANOTW AORB AORL AORPD AORPS
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 16.3K bytes - Viewed (0) -
src/runtime/sys_freebsd_amd64.s
MOVL $SYS_clock_gettime, AX MOVQ $CLOCK_MONOTONIC, DI LEAQ 8(SP), SI SYSCALL MOVQ 8(SP), AX // sec MOVQ 16(SP), DX // nsec // sec is in AX, nsec in DX // return nsec in AX IMULQ $1000000000, AX ADDQ DX, AX MOVQ AX, ret+0(FP) RET TEXT runtime·asmSigaction(SB),NOSPLIT,$0 MOVQ sig+0(FP), DI // arg 1 sig MOVQ new+8(FP), SI // arg 2 act MOVQ old+16(FP), DX // arg 3 oact
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 12.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
IMUL3L $7, R11, R11 // 456bdb07 IMULQ (BX), DX // 480faf13 IMULQ (R11), DX // 490faf13 IMULQ DX, DX // 480fafd2 IMULQ R11, DX // 490fafd3 IMULQ (BX), R11 // 4c0faf1b IMULQ (R11), R11 // 4d0faf1b IMULQ DX, R11 // 4c0fafda
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 08 21:38:44 UTC 2021 - 581.9K bytes - Viewed (0) -
src/runtime/sys_linux_amd64.s
// we cannot receive another signal. MOVQ 8(SP), CX MOVQ CX, m_vdsoSP(BX) MOVQ 0(SP), CX MOVQ CX, m_vdsoPC(BX) // sec is in AX, nsec in DX // return nsec in AX IMULQ $1000000000, AX ADDQ DX, AX MOVQ AX, ret+0(FP) RET fallback: MOVQ $SYS_clock_gettime, AX SYSCALL JMP ret TEXT runtime·rtsigprocmask(SB),NOSPLIT,$0-28 MOVL how+0(FP), DI
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 24 18:53:44 UTC 2023 - 15.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// (ANDQconst [0xFFFFFFFF] x) => (MOVLQZX x) // strength reduction // Assumes that the following costs from https://gmplib.org/~tege/x86-timing.pdf: // 1 - addq, shlq, leaq, negq, subq // 3 - imulq // This limits the rewrites to two instructions. // Note that negq always operates in-place, // which can require a register-register move // to preserve the original value, // so it must be used with care.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
{AMPSADBW, yxshuf, Pq, opBytes{0x3a, 0x42, 0}}, {AMULB, ydivb, Pb, opBytes{0xf6, 04}}, {AMULL, ydivl, Px, opBytes{0xf7, 04}}, {AMULPD, yxm, Pe, opBytes{0x59}}, {AMULPS, yxm, Ym, opBytes{0x59}}, {AMULQ, ydivl, Pw, opBytes{0xf7, 04}}, {AMULSD, yxm, Pf2, opBytes{0x59}}, {AMULSS, yxm, Pf3, opBytes{0x59}}, {AMULW, ydivl, Pe, opBytes{0xf7, 04}}, {ANEGB, yscond, Pb, opBytes{0xf6, 03}},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0)