//	}
	SLL	R1, R2

	//	LSHW imm ',' sreg ',' rreg
	//	{
	//		outcode(int($1), &$2, int($4), &$6);
	//	}
	SLL	$4, R1, R2

	//	LSHW imm ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	SLL	$4, R1

	//
	// move immediate: macro for lui+or, addi, addis, and other combinations
	//
	//	LMOVW imm ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}

	ROTRV	R16, R9		// 02094856

//	LSHW imm ',' sreg ',' rreg
//	{
//		outcode(int($1), &$2, int($4), &$6);
//	}
	SLL	$19, R22, R21	// 0016acc0
	SLLV	$19, R22, R21	// 0016acf8
	SRL	$31, R6, R17	// 00068fc2
	SRLV	$31, R6, R17	// 00068ffa
	SRA	$8, R8, R19	// 00089a03
	SRAV	$19, R8, R7	// 00083cfb
	ROTR	$12, R8, R3	// 00281b02
	ROTRV	$8, R22, R22	// 0036b23a

//	LSHW imm ',' rreg
//	{

				}
			}
		}
	}

	switch inst.Op {
	case AAM, AAD:
		if imm, ok := iargs[0].(Imm); ok {
			if inst.DataSize == 32 {
				iargs[0] = Imm(uint32(int8(imm)))
			} else if inst.DataSize == 16 {
				iargs[0] = Imm(uint16(int8(imm)))
			}
		}

	case PUSH:
		if imm, ok := iargs[0].(Imm); ok {
			iargs[0] = Imm(uint32(imm))
		}
	}

	for _, p := range inst.Prefix {
		if p&PrefixImplicit != 0 {

			}
		}
	}
}

// An Imm is an integer constant.
type Imm struct {
	Imm     uint32
	Decimal bool
}

func (Imm) isArg() {}

func (i Imm) String() string {
	if !i.Decimal {
		return fmt.Sprintf("#%#x", i.Imm)
	} else {
		return fmt.Sprintf("#%d", i.Imm)
	}
}

type Imm64 struct {
	Imm     uint64
	Decimal bool
}

func (Imm64) isArg() {}

			op = "int3"
		}

	case CMPPS, CMPPD, CMPSD_XMM, CMPSS:
		imm, ok := inst.Args[2].(Imm)
		if ok && 0 <= imm && imm < 8 {
			inst.Args[2] = nil
			op = cmppsOps[imm] + op[3:]
		}

	case PCLMULQDQ:
		imm, ok := inst.Args[2].(Imm)
		if ok && imm&^0x11 == 0 {
			inst.Args[2] = nil
			op = pclmulqOps[(imm&0x10)>>3|(imm&1)]
		}

	case XLATB:
		if markLastImplicit(&inst, PrefixAddrSize) {

{"Name":"DCPS1","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|0|1","Arch":"System variant","Syntax":"DCPS1 {#<imm>}","Code":"","Alias":""},
{"Name":"DCPS2","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|0","Arch":"System variant","Syntax":"DCPS2 {#<imm>}","Code":"","Alias":""},
{"Name":"DCPS3","Bits":"1|1|0|1|0|1|0|0|1|0|1|imm16:16|0|0|0|1|1","Arch":"System variant","Syntax":"DCPS3 {#<imm>}","Code":"","Alias":""},

type Rel int32

func (Rel) isArg() {}

func (r Rel) String() string {
	return fmt.Sprintf(".%+d", r)
}

// An Imm is an integer constant.
type Imm int64

func (Imm) isArg() {}

func (i Imm) String() string {
	return fmt.Sprintf("%#x", int64(i))
}

func (i Inst) String() string {
	var buf bytes.Buffer
	for _, p := range i.Prefix {
		if p == 0 {

	// CMN <Wn|WSP>, #<imm>{, <shift>}
	{0xff00001f, 0x3100001f, CMN, instArgs{arg_Wns, arg_IAddSub}, nil},
	// ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
	{0xff000000, 0x31000000, ADDS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil},
	// CMN <Xn|SP>, #<imm>{, <shift>}
	{0xff00001f, 0xb100001f, CMN, instArgs{arg_Xns, arg_IAddSub}, nil},
	// ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}

		case xArgImm8:
			inst.Args[narg] = Imm(imm8)
			narg++

		case xArgImm8u:
			inst.Args[narg] = Imm(uint8(imm8))
			narg++

		case xArgImm16:
			inst.Args[narg] = Imm(int16(imm))
			narg++

		case xArgImm16u:
			inst.Args[narg] = Imm(uint16(imm))
			narg++

		case xArgImm32:
			inst.Args[narg] = Imm(int32(imm))
			narg++

		case xArgImm64:

		}
		return op + " (" + args[1] + ")(" + args[0] + ")"

	// branch instructions needs additional handling
	case BCLR:
		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
			return "RET"
		}
		return op + " " + strings.Join(args, ", ")
	case BC:
		bo := int(inst.Args[0].(Imm))
		bi := int(inst.Args[1].(CondReg) - Cond0LT)
		bcname := condName[((bo&0x8)>>1)|(bi&0x3)]