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Results 81 - 90 of 104 for lowerings (0.18 sec)

  1. analysis/analysis-api-fir/src/org/jetbrains/kotlin/analysis/api/fir/components/KtFirCompilerFacility.kt

                    // generated, which requires a container source to be provided. Without a facade class, function IR symbols will have
                    // an `IrExternalPackageFragment` parent, which trips up code generation during IR lowering.
                    val psiSourceFile =
                        descriptor.toSourceElement.containingFile as? PsiSourceFile ?: return super.getContainerSource(descriptor)
    Registered: Wed Jun 12 09:53:16 UTC 2024
    - Last Modified: Wed Jun 05 08:42:45 UTC 2024
    - 29.4K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/transforms/passes.td

            "When specified to true, if the tensorlist ops has unspecified batch "
            "size, this pass will assume that the batch size is one to proceed "
            "tensorlist op lowering (default true)">,
          Option<"enable_dynamic_update_slice_", "enable-dynamic-update-slice",
                 "bool", "false", "When specified to true, lower TensorListSetItem with "
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Apr 24 20:30:06 UTC 2024
    - 22.6K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/compile.go

    	// the rules in late lower run after the general rules.
    	{"lower", "late lower"},
    	// late lower may generate some values that need to be CSEed.
    	{"late lower", "lowered cse"},
    	// checkLower must run after lowering & subsequent dead code elim
    	{"lower", "checkLower"},
    	{"lowered deadcode", "checkLower"},
    	{"late lower", "checkLower"},
    	// late nilcheck needs instructions to be scheduled.
    	{"schedule", "late nilcheck"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 22 14:55:18 UTC 2024
    - 18.6K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/transforms/host_runtime/tpu_rewrite_pass.cc

      // TODO(b/157054714): When a better abstraction instead of _TPUCompileMlirOp
      // and _XlaRecvAtHostOp and _XlaSendFromHostOp are used, update to a more
      // structured lowering.
      old_parallel_execute.walk(
          [&](TF::_XlaCompileMlirPlaceholderProgramKeyOp key_op) {
            key_op.replaceAllUsesWith(compile_op->getResult(1));
            key_op.erase();
          });
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Apr 30 21:25:12 UTC 2024
    - 29.7K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/quantization/stablehlo/passes/bridge/convert_tf_quant_ops_to_mhlo.cc

    template <typename UniformQuantizedConvolutionOp>
    FailureOr<SmallVector<NamedAttribute>> ConvertToMhloConvolutionOpAttrs(
        UniformQuantizedConvolutionOp op, PatternRewriter &rewriter) {
      // TODO(b/261005147): Update the lowering logic after migration to mhlo
      // ConvolutionDimensionNumbers.
      ::tensorflow::UniformQuantizedConvolutionDimensionNumbersAttr dnums_input;
      if (!dnums_input.ParseFromString(std::string(op.getDimensionNumbers()))) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 17 17:58:54 UTC 2024
    - 30.9K bytes
    - Viewed (0)
  6. tensorflow/compiler/aot/tests/tfcompile_test.cc

    #include "tensorflow/compiler/aot/tests/test_graph_tfvariable_readonly_mlir_bridge.h"
    #include "tensorflow/compiler/aot/tests/test_graph_tfvariable_sequential_updates_mlir_bridge.h"
    // Similarly, there are files for testing the MLIR based lowering of HLO to
    // object code for XLA:CPU
    #elif defined(MHLO_LOWERING_TEST)
    #include "tensorflow/compiler/aot/tests/test_graph_tfadd_mhlo_lowering.h"
    #include "tensorflow/compiler/aot/tests/test_graph_tfadd_with_ckpt_mhlo_lowering.h"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Sep 06 19:12:29 UTC 2023
    - 26.4K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "LoweredAtomicOr32", argLength: 3, reg: gpatomic, asm: "AMOORW", faultOnNilArg0: true, hasSideEffects: true},
    
    		// Lowering pass-throughs
    		{name: "LoweredNilCheck", argLength: 2, faultOnNilArg0: true, nilCheck: true, reg: regInfo{inputs: []regMask{gpspMask}}}, // arg0=ptr,arg1=mem, returns void.  Faults if ptr is nil.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  8. pkg/controller/replicaset/replica_set_test.go

    		t.Fatal(err)
    	}
    
    	// Get the key for the controller
    	rsKey, err := controller.KeyFunc(rsSpec)
    	if err != nil {
    		t.Errorf("Couldn't get key for object %#v: %v", rsSpec, err)
    	}
    
    	// Lowering expectations should lead to a sync that creates a replica, however the
    	// fakePodControl error will prevent this, leaving expectations at 0, 0
    	manager.expectations.CreationObserved(logger, rsKey)
    	rsSpec.Status.Replicas = 1
    Registered: Sat Jun 15 01:39:40 UTC 2024
    - Last Modified: Sat May 04 18:33:12 UTC 2024
    - 69.2K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf_communication.cc

    See the License for the specific language governing permissions and
    limitations under the License.
    ==============================================================================*/
    
    // This file implements logic for lowering TensorFlow dialect's communication
    // ops (TF/XLA) to the HLO dialect.
    
    #include <atomic>
    #include <cstddef>
    #include <cstdint>
    #include <memory>
    #include <optional>
    #include <string>
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 25 16:01:03 UTC 2024
    - 40.5K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/ARMOps.go

    		{name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"},  // float32 -> float64
    		{name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"},  // float64 -> float32
    
    		// conditional instructions, for lowering shifts
    		{name: "CMOVWHSconst", argLength: 2, reg: gp1flags1, asm: "MOVW", aux: "Int32", resultInArg0: true}, // replace arg0 w/ const if flags indicates HS, arg1=flags
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 41K bytes
    - Viewed (0)
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