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Results 51 - 60 of 116 for lowering (0.17 sec)
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src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go
{name: "LoweredAtomicOr32", argLength: 3, reg: gpatomic, asm: "AMOORW", faultOnNilArg0: true, hasSideEffects: true}, // Lowering pass-throughs {name: "LoweredNilCheck", argLength: 2, faultOnNilArg0: true, nilCheck: true, reg: regInfo{inputs: []regMask{gpspMask}}}, // arg0=ptr,arg1=mem, returns void. Faults if ptr is nil.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 30.7K bytes - Viewed (0) -
pkg/controller/replicaset/replica_set_test.go
t.Fatal(err) } // Get the key for the controller rsKey, err := controller.KeyFunc(rsSpec) if err != nil { t.Errorf("Couldn't get key for object %#v: %v", rsSpec, err) } // Lowering expectations should lead to a sync that creates a replica, however the // fakePodControl error will prevent this, leaving expectations at 0, 0 manager.expectations.CreationObserved(logger, rsKey) rsSpec.Status.Replicas = 1
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Sat May 04 18:33:12 UTC 2024 - 69.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc
See the License for the specific language governing permissions and limitations under the License. ==============================================================================*/ // This file implements logic for lowering TensorFlow dialect to XLA dialect. #include <algorithm> #include <cctype> #include <cmath> #include <cstddef> #include <cstdint> #include <iterator> #include <limits> #include <numeric> #include <optional>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 291.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf_communication.cc
See the License for the specific language governing permissions and limitations under the License. ==============================================================================*/ // This file implements logic for lowering TensorFlow dialect's communication // ops (TF/XLA) to the HLO dialect. #include <atomic> #include <cstddef> #include <cstdint> #include <memory> #include <optional> #include <string>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 40.5K bytes - Viewed (0) -
src/cmd/link/link_test.go
November weather. As much mud in the streets as if the waters had but newly retired from the face of the earth, and it would not be wonderful to meet a Megalosaurus, forty feet long or so, waddling like an elephantine lizard up Holborn Hill. Smoke lowering down from chimney-pots, making a soft black drizzle, with flakes of soot in it as big as full-grown snowflakes—gone into mourning, one might imagine, for the death of the sun. Dogs, undistinguishable in mire. Horses, scarcely better; splashed to...
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 24 20:26:02 UTC 2024 - 43.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/lower_static_tensor_list.cc
if (!this->allow_tensorlist_pass_through_) { if (failed(applyPartialConversion(module, target, std::move(patterns)))) { module.emitError( "Lowering tensor list ops is failed. Please consider using Select TF " "ops and disabling `_experimental_lower_tensor_list_ops` flag in the " "TFLite converter object. For example, "
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 70.7K bytes - Viewed (0) -
src/runtime/asm_ppc64x.s
// register (R5), and the unwinder currently doesn't understand. // Make it SPWRITE to stop unwinding. (See issue 54332) // Use OR R0, R1 instead of MOVD R1, R1 as the MOVD instruction // has a special affect on Power8,9,10 by lowering the thread // priority and causing a slowdown in execution time OR R0, R1 MOVD R0, R11 BR runtime·morestack(SB) // reflectcall: call a function with the given argument list
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 45.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(RoundToEven ...) => (FRINTND ...) (Trunc ...) => (FRINTZD ...) (FMA x y z) => (FMADDD z x y) (Sqrt32 ...) => (FSQRTS ...) (Min(64|32)F ...) => (FMIN(D|S) ...) (Max(64|32)F ...) => (FMAX(D|S) ...) // lowering rotates // we do rotate detection in generic rules, if the following rules need to be changed, check generic rules first.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/optimize.cc
if (is_output_shape_dynamic && is_broadcast_shape_dynamic) return rewriter.notifyMatchFailure( loc, "output_rank or broadcast_to shape not supported"); // Allow lowering when the input's elements type is F32, BFloat16, I32 or // I16. if (!(mlir::isa<BFloat16Type, Float32Type>(element_type) || element_type.isInteger(32) || element_type.isInteger(16)))
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Apr 30 00:40:15 UTC 2024 - 102.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
// of this conversion is: // a' = (ADDCC x y) // a = (Select0 a') // b = (CMPconst [0] a) // c = (OR a z) // // Which makes it trivial to rewrite b using a lowering rule. func convertPPC64OpToOpCC(op *Value) *Value { ccOpMap := map[Op]Op{ OpPPC64ADD: OpPPC64ADDCC, OpPPC64ADDconst: OpPPC64ADDCCconst, OpPPC64AND: OpPPC64ANDCC,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0)