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Results 1 - 10 of 14 for fmadd (0.06 sec)
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src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true}, // arg0*arg1 {name: "FMADD", argLength: 3, reg: fp31, asm: "FMADD"}, // arg0*arg1 + arg2 {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS"}, // arg0*arg1 + arg2 {name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB"}, // arg0*arg1 - arg2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
FDIVSCC F1, F2, F3 // ec620825 FTDIV F1, F2, $2 // fd011100 FTSQRT F1, $2 // fd000940 FMADD F1, F2, F3, F4 // fc8110fa FMADDCC F1, F2, F3, F4 // fc8110fb FMADDS F1, F2, F3, F4 // ec8110fa FMADDSCC F1, F2, F3, F4 // ec8110fb FMSUB F1, F2, F3, F4 // fc8110f8 FMSUBCC F1, F2, F3, F4 // fc8110f9
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(Sqrt32 ...) => (FSQRTS ...) (Floor ...) => (FFLOOR ...) (Ceil ...) => (FCEIL ...) (Trunc ...) => (FTRUNC ...) (Round ...) => (FROUND ...) (Copysign x y) => (FCPSGN y x) (Abs ...) => (FABS ...) (FMA ...) => (FMADD ...) // Lowering extension // Note: we always extend to 64 bits even though some ops don't need that many result bits. (SignExt8to(16|32|64) ...) => (MOVBreg ...) (SignExt16to(32|64) ...) => (MOVHreg ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(MADD a (MOVDconst [-1]) x) => (SUB a x) (MADD a (MOVDconst [0]) _) => a (MADD a (MOVDconst [1]) x) => (ADD a x) (MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c) => (ADDshiftLL a x [log64(c)]) (MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)])) (MADD a (MOVDconst [c]) x) && isPowerOfTwo64(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true}, // 3-operand, the addend comes first {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS"}, // +arg0 + (arg1 * arg2) {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD"}, // +arg0 + (arg1 * arg2) {name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS"}, // -arg0 - (arg1 * arg2)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
rel.Off = int32(c.pc) rel.Siz = 4 rel.Sym = p.To.Sym rel.Add = p.To.Offset rel.Type = objabi.R_ADDR o1 = 0 } case 15: /* mul/mneg/umulh/umull r,[r,]r; madd/msub/fmadd/fmsub/fnmadd/fnmsub Rm,Ra,Rn,Rd */ o1 = c.oprrr(p, p.As) rf := int(p.From.Reg) rt := int(p.To.Reg) var r int var ra int if p.From3Type() == obj.TYPE_REG { r = int(p.GetFrom3().Reg)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
return true } return false } func rewriteValuePPC64_OpPPC64FADD(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] // match: (FADD (FMUL x y) z) // cond: x.Block.Func.useFMA(v) // result: (FMADD x y z) for { for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 { if v_0.Op != OpPPC64FMUL { continue } _ = v_0.Args[1] v_0_0 := v_0.Args[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
test/codegen/arithmetic.go
// arm:`MULA`,-`MUL\s` // arm64:`MADDW`,-`MULW` r0 := a*b + c // arm:`MULA`,-`MUL\s` // arm64:`MADDW`,-`MULW` r1 := c*79 + a // arm:`ADD`,-`MULA`,-`MUL\s` // arm64:`ADD`,-`MADD`,-`MULW` // ppc64x:`ADD`,-`MULLD` r2 := b*64 + c return r0, r1, r2 } func MULS(a, b, c uint32) (uint32, uint32, uint32) { // arm/7:`MULS`,-`MUL\s` // arm/6:`SUB`,`MUL\s`,-`MULS`
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/asm.go
AAMCASB: 0x070B0 << 15, // amcas.b AAMCASH: 0x070B1 << 15, // amcas.h AAMCASW: 0x070B2 << 15, // amcas.w AAMCASV: 0x070B3 << 15, // amcas.d AAMADDW: 0x070C2 << 15, // amadd.w AAMADDV: 0x070C3 << 15, // amadd.d AAMANDW: 0x070C4 << 15, // amand.w AAMANDV: 0x070C5 << 15, // amand.d AAMORW: 0x070C6 << 15, // amor.w AAMORV: 0x070C7 << 15, // amor.d AAMXORW: 0x070C8 << 15, // amxor.w
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 61.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 }, }, }, { name: "FMADD", argLen: 3, asm: ppc64.AFMADD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)