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src/crypto/sha512/sha512block_amd64.s
XORQ R12, R14 MOVQ R9, R12 ANDQ R11, R12 ORQ R12, DI ADDQ R14, DX ADDQ R15, DX ADDQ DI, DX VPADDQ 3*32(BP), Y7, Y0 VMOVDQU Y0, frame_YFER(SP) ADDQ $(4*32), BP MY_VPALIGNR(Y0, Y6, Y5, 8) VPADDQ Y7, Y0, Y0 MY_VPALIGNR(Y1, Y4, Y7, 8) VPSRLQ $1, Y1, Y2 VPSLLQ $(64-1), Y1, Y3 VPOR Y2, Y3, Y3 VPSRLQ $7, Y1, Y8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 27K bytes - Viewed (0) -
src/main/java/jcifs/smb/SmbTransportImpl.java
return null; } if ( log.isTraceEnabled() ) { log.trace("New data read: " + this); log.trace(Hexdump.toHexString(this.sbuf, 4, 32)); } for ( ;; ) { /* * 01234567 * 00SSFSMB * 0 - 0's * S - size of payload * FSMB - 0xFF SMB magic #
Registered: Wed Jun 12 15:45:55 UTC 2024 - Last Modified: Wed Jan 18 23:47:00 UTC 2023 - 67K bytes - Viewed (0) -
go.sum
github.com/DataDog/datadog-go v3.2.0+incompatible/go.mod h1:LButxg5PwREeZtORoXG3tL4fMGNddJ+vMq1mwgfaqoQ= github.com/IBM/sarama v1.43.2 h1:HABeEqRUh32z8yzY2hGB/j8mHSzC/HA9zlEjqFNCzSw= github.com/IBM/sarama v1.43.2/go.mod h1:Kyo4WkF24Z+1nz7xeVUFWIuKVV8RS3wM8mkvPKMdXFQ= github.com/VividCortex/ewma v1.2.0 h1:f58SaIzcDXrSy3kWaHNvuJgJ3Nmz59Zji6XoJR/q1ow=
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Thu Jun 13 22:53:53 UTC 2024 - 85.8K bytes - Viewed (0) -
src/cmd/compile/internal/test/testdata/arith_test.go
} w8 := uint64(0x0807060504030201) g8 := uint64(loadSymData[0]) | uint64(loadSymData[1])<<8 | uint64(loadSymData[2])<<16 | uint64(loadSymData[3])<<24 | uint64(loadSymData[4])<<32 | uint64(loadSymData[5])<<40 | uint64(loadSymData[6])<<48 | uint64(loadSymData[7])<<56 if g8 != w8 { t.Errorf("testLoadSymCombine failed, wanted %d got %d", w8, g8) } } //go:noinline
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 01 19:30:59 UTC 2023 - 43.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/telemetry/package-lock.json
"integrity": "sha512-+5gy6OQfk+xx3q0d6jGZZC3f3KzAkXc/IanVxd1is/VIIziRqqt3ongQz0FiTUXqTk0c7aDB3OaFuKnuSoJicQ==", "dev": true, "dependencies": { "ajv": "^6.12.4", "debug": "^4.3.2", "espree": "^9.5.2", "globals": "^13.19.0", "ignore": "^5.2.0", "import-fresh": "^3.2.1", "js-yaml": "^4.1.0", "minimatch": "^3.1.2",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:57:25 UTC 2024 - 156K bytes - Viewed (1) -
src/crypto/sha256/sha256block_amd64.s
ROUND_AND_SCHED_N_2(_XFER + 3*32, c, d, e, f, g, h, a, b, XDWORD3, XDWORD0, XDWORD1, XDWORD2) ROUND_AND_SCHED_N_3(_XFER + 3*32, b, c, d, e, f, g, h, a, XDWORD3, XDWORD0, XDWORD1, XDWORD2) ADDQ $4*32, SRND CMPQ SRND, $3*4*32 JB avx2_loop1 avx2_loop2: // w48 - w63 processed with no scheduling (last 16 rounds) VPADDD 0*32(TBL)(SRND*1), XDWORD0, XFER VMOVDQU XFER, (_XFER + 0*32)(SP)(SRND*1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 47.3K bytes - Viewed (0) -
src/crypto/internal/nistec/fiat/p384_fiat64.go
// // // // Computed values: // // eval z = z[0] + (z[1] << 64) + (z[2] << 128) + (z[3] << 192) + (z[4] << 256) + (z[5] << 0x140) //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 05 21:53:03 UTC 2022 - 90.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/fuse-tftext.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 460.3K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/sys/unix/zsysnum_zos_s390x.go
SYS_OPENDIR = 0x1AD // 429 SYS_PATHCONF = 0x1AE // 430 SYS_PAUSE = 0x1AF // 431 SYS_PIPE = 0x1B0 // 432 SYS_W_GETPSENT = 0x1B1 // 433 SYS_READ = 0x1B2 // 434 SYS_READDIR = 0x1B3 // 435 SYS_READLINK = 0x1B4 // 436
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 08 16:12:58 UTC 2024 - 146.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// For DCBT Ra,Rb,TH, A value of TH indicates: // 0, hint this cache line will be used soon. (PrefetchCache) // 16, hint this cache line will not be used for long. (PrefetchCacheStreamed) // See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/ (PrefetchCache ptr mem) => (DCBT ptr mem [0]) (PrefetchCacheStreamed ptr mem) => (DCBT ptr mem [16]) // Use byte reverse instructions on Power10
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0)