(S(LD|RD|RAD|LW|RW|RAW) x (ANDWconst [c] y)) && c&63 == 63
  => (S(LD|RD|RAD|LW|RW|RAW) x y)
(SLD  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SLD  x y)
(SRD  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRD  x y)
(SRAD x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRAD x y)
(SLW  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SLW  x y)
(SRW  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRW  x y)
(SRAW x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRAW x y)

// Match rotate by constant.

Go compiler will add appropriate code to compare the shift value to achieve the
correct result, and the assembler does not add extra checking.

Examples:

	SRAD $8,R3,R4		=>	sradi r4,r3,8
	SRD $8,R3,R4		=>	rldicl r4,r3,56,8
	SLD $8,R3,R4		=>	rldicr r4,r3,8,55
	SRAW $16,R4,R5		=>	srawi r5,r4,16
	SRW $40,R4,R5		=>	rlwinm r5,r4,0,0,31
	SLW $12,R4,R5		=>	rlwinm r5,r4,12,0,19

TEXT	·erfcAsm(SB), NOSPLIT|NOFRAME, $0-16
	MOVD	x+0(FP), R1
	MOVD	$Neg2p11, R2
	CMPUBGT	R1, R2, usego

	FMOVD	x+0(FP), F0
	MOVD	$·erfcrodataL38<>+0(SB), R9
	FMOVD	F0, F2
	SRAD	$48, R1
	MOVH	R1, R2
	ANDW	$0x7FFF, R1
	MOVH	$Pos15, R3
	CMPW	R1, R3
	BGT	usego
	MOVH	$0x3FFF, R3
	MOVW	R1, R6
	MOVW	R3, R7
	CMPBGT	R6, R7, L2
	MOVH	$0x3FEF, R3
	MOVW	R3, R7

	WFMADB	V3, V1, V5, V1
	MOVD	$·powtexp<>+0(SB), R3
	WORD	$0x68343000	//ld	%f3,0(%r4,%r3)
	FMADD	F3, F4, F4
	RISBGN	$0, $15, $48, R2, R5
	WFMADB	V4, V1, V3, V4
	LGDR	F6, R2
	LDGR	R5, F1
	SRAD	$48, R2, R2
	FMADD	F1, F4, F1
	RLL	$16, R2, R2
	ANDW	$0x7FFF0000, R2
	WORD	$0xC22B3F71	//alfi	%r2,1064370176
	BYTE	$0x00
	BYTE	$0x00
	ORW	R2, R1, R3
	MOVW	R3, R6
	CMPBLT	R6, $0, L43
L1:

	VCVTPS2PH $-1, X1, X2        // c4e3791dcaff
	VCVTPS2PH $-1, Y1, X2        // c4e37d1dcaff
	VPSLLW $-1, X1, X2           // c5e971f1ff
	VPSLLW $-1, Y1, Y2           // c5ed71f1ff
	VPSRAD $-1, X1, X2           // c5e972e1ff
	VPSRAD $-1, Y1, Y2           // c5ed72e1ff
	VPSRAW $-1, X1, X2           // c5e971e1ff
	VPSRAW $-1, Y1, Y2           // c5ed71e1ff
	VPSRLW $-1, X1, X1           // c5f171d1ff

	ADD     $-2, R4, R16
	PCALIGN $16
loopback:
	ADD     $-1, R8, R10
	SLD     $3, R10
	LXVD2X  (R6)(R10), VS32 // load x[i-1], x[i]
	SLD     $3, R8, R12
	LXVD2X  (R6)(R12), VS33 // load x[i], x[i+1]

	VSRD    V0, V4, V3      // x[i-1]>>s, x[i]>>s
	VSLD    V1, V2, V5      // x[i]<<ŝ, x[i+1]<<ŝ
	VOR     V3, V5, V5      // Or(|) the two registers together
	STXVD2X VS37, (R3)(R10) // store into z[i-1] and z[i]

	VADDUBM  XC2, XC2, XC2       // 0xc2...
	VSPLTISB $7, T2
	VOR      XC2, T1, XC2        // 0xc2....01
	VSPLTB   $0, H, T1           // most significant byte
	VSL      H, T0, H            // H<<=1
	VSRAB    T1, T2, T1          // broadcast carry bit
	VAND     T1, XC2, T1
	VXOR     H, T1, IN           // twisted H

	VSLDOI $8, IN, IN, H      // twist even more ...
	VSLDOI $8, ZERO, XC2, XC2 // 0xc2.0

	/*4834*/ uint16(xMatch),
	/*4835*/ uint16(xCondPrefix), 2,
	0x66, 4847,
	0x0, 4841,
	/*4841*/ uint16(xSetOp), uint16(PSRAD),
	/*4843*/ uint16(xReadIb),
	/*4844*/ uint16(xArgMm2),
	/*4845*/ uint16(xArgImm8u),
	/*4846*/ uint16(xMatch),
	/*4847*/ uint16(xSetOp), uint16(PSRAD),
	/*4849*/ uint16(xReadIb),
	/*4850*/ uint16(xArgXmm2),
	/*4851*/ uint16(xArgImm8u),
	/*4852*/ uint16(xMatch),

	"XSCMPGTQP",
	"XSCMPGEQP",
	"XSCMPEQQP",
	"VSTRIHRCC",
	"VSTRIHR",
	"VSTRIHLCC",
	"VSTRIHL",
	"VSTRIBRCC",
	"VSTRIBR",
	"VSTRIBLCC",
	"VSTRIBL",
	"VSRQ",
	"VSRDBI",
	"VSRAQ",
	"VSLQ",
	"VSLDBI",
	"VRLQNM",
	"VRLQMI",
	"VRLQ",
	"VPEXTD",
	"VPDEPD",
	"VMULOUD",
	"VMULOSD",
	"VMULLD",
	"VMULHUW",
	"VMULHUD",
	"VMULHSW",
	"VMULHSD",
	"VMULEUD",

		case AAND:
			opset(AOR, r)
			opset(AXOR, r)
		case AANDW:
			opset(AORW, r)
			opset(AXORW, r)
		case ASLD:
			opset(ASRD, r)
			opset(ASLW, r)
			opset(ASRW, r)
			opset(ASRAD, r)
			opset(ASRAW, r)
			opset(ARLL, r)
			opset(ARLLG, r)
		case ARNSBG:
			opset(ARXSBG, r)
			opset(AROSBG, r)
			opset(ARNSBGT, r)
			opset(ARXSBGT, r)
			opset(AROSBGT, r)