// Non-indexed ops generate DS-form loads and stores when the offset fits in 16 bits,
// and on power8 and power9, a multiple of 4 is required for MOVW and MOVD ops.
// On power10, prefixed loads and stores can be used for offsets > 16 bits and <= 32 bits.
// and support for PC relative addressing must be available if relocation is needed.
// On power10, the assembler will determine when to use DS-form or prefixed

#ifdef GOARCH_ppc64le
#  ifdef GOPPC64_power9
#define P8_LXVB16X(RA,RB,VT)  LXVB16X	(RA+RB), VT
#define P8_STXVB16X(VS,RA,RB) STXVB16X	VS, (RA+RB)
#define XXBRD_ON_LE(VA,VT)    XXBRD	VA, VT
#  else
// On POWER8/ppc64le, emulate the POWER9 instructions by loading unaligned
// doublewords and byte-swapping each doubleword to emulate BE load/stores.
#define NEEDS_ESPERM
#define P8_LXVB16X(RA,RB,VT) \
	LXVD2X	(RA+RB), VT \
	VPERM	VT, VT, ESPERM, VT

		bytesPerLoop := int64(64)
		// This is used when moving more
		// than 8 bytes on power9.  Moves start with
		// as many 8 byte moves as possible, then
		// 4, 2, or 1 byte(s) as remaining.  This will
		// work and be efficient for power8 or later.
		// If there are 64 or more bytes, then a
		// loop is generated to move 32 bytes and
		// update the src and dst addresses on each

#define VH4    VS62
#define VH4H   VS63

#define VIN0   VIN

#define ESPERM V10
#define TMP2 V11

// The following macros provide appropriate
// implementations for endianness as well as
// ISA specific for power8 and power9.
#ifdef GOARCH_ppc64le
#  ifdef GOPPC64_power9
#define P8_LXVB16X(RA,RB,VT)   LXVB16X (RA)(RB), VT
#define P8_STXVB16X(VS,RA,RB)  STXVB16X VS, (RA)(RB)
#  else
#define NEEDS_ESPERM

		"loong64": {},
		"mips":    {"GOMIPS", "hardfloat", "softfloat"},
		"mips64":  {"GOMIPS64", "hardfloat", "softfloat"},
		"ppc64":   {"GOPPC64", "power8", "power9", "power10"},
		"ppc64le": {"GOPPC64", "power8", "power9", "power10"},
		"ppc64x":  {}, // A pseudo-arch representing both ppc64 and ppc64le
		"s390x":   {},
		"wasm":    {},
		"riscv64": {"GORISCV64", "rva20u64", "rva22u64"},
	}
)

	// Hex constant 0x20004000000
	MOVD $2199090364416, R5         // 60058001
	// Hex constant 0xFFFFFE0004000000
	MOVD $-2198956146688, R5        // 38a08001
	// TODO: On GOPPC64={power8,power9}, this is preprocessed into MOVD $-1, R5; RLDC R5, $33, $63, R5.
	//       This only captures the MOVD. Should the RLDC be appended to the encoding by the test?
	// Hex constant 0xFFFFFFFE00000001

//     (or mips64le.hardfloat and mips64le.softfloat) feature build tags.
//   - For GOARCH=ppc64 or ppc64le,
//     GOPPC64=power8, power9, and power10 correspond to the
//     ppc64.power8, ppc64.power9, and ppc64.power10
//     (or ppc64le.power8, ppc64le.power9, and ppc64le.power10)
//     feature build tags.
//   - For GOARCH=riscv64,
//     GORISCV64=rva20u64 and rva22u64 correspond to the riscv64.rva20u64

	}
	if goarch == "ppc64" || goarch == "ppc64le" {
		// We treat each powerpc version as a superset of functionality.
		switch goppc64 {
		case "power10":
			asmArgs = append(asmArgs, "-D", "GOPPC64_power10")
			fallthrough
		case "power9":
			asmArgs = append(asmArgs, "-D", "GOPPC64_power9")
			fallthrough
		default: // This should always be power8.
			asmArgs = append(asmArgs, "-D", "GOPPC64_power8")
		}
	}

}

// Power-series constructors return channels on which power
// series flow.  They start an encapsulated generator that
// puts the terms of the series on the channel.

// Make a pair of power series identical to a given power series

func Split(U PS) *dch2 {
	UU := mkdch2()
	go split(U, UU)
	return UU
}

// Add two power series
func Add(U, V PS) PS {
	Z := mkPS()

}

// Power-series constructors return channels on which power
// series flow.  They start an encapsulated generator that
// puts the terms of the series on the channel.

// Make a pair of power series identical to a given power series

func Split(U PS) *dch2 {
	UU := mkdch2()
	go split(U, UU)
	return UU
}

// Add two power series
func Add(U, V PS) PS {
	Z := mkPS()