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src/compress/flate/testdata/huffman-shifts.wb.expect
Klaus Post <******@****.***> 1457448890 +0100
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 11 17:40:52 UTC 2016 - 32 bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/dec64.rules
(Rsh64x64 [c] x (Int64Make (Const32 [0]) lo)) => (Rsh64x32 [c] x lo) (Rsh64Ux64 [c] x (Int64Make (Const32 [0]) lo)) => (Rsh64Ux32 [c] x lo) // turn x64 non-constant shifts to x32 shifts // if high 32-bit of the shift is nonzero, make a huge shift (Lsh64x64 x (Int64Make hi lo)) && hi.Op != OpConst32 => (Lsh64x32 x (Or32 <typ.UInt32> (Zeromask hi) lo)) (Rsh64x64 x (Int64Make hi lo)) && hi.Op != OpConst32 =>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Oct 04 19:35:46 UTC 2022 - 14.2K bytes - Viewed (0) -
src/strconv/itoa.go
// the compiler to generate better code for the shift operation. shift := uint(bits.TrailingZeros(uint(base))) & 7 b := uint64(base) m := uint(base) - 1 // == 1<<shift - 1 for u >= b { i-- a[i] = digits[uint(u)&m] u >>= shift } // u < base i-- a[i] = digits[uint(u)] } else { // general case b := uint64(base) for u >= b { i--
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 14:21:28 UTC 2024 - 5.3K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/doc.go
specified alignment. 6. Shift instructions The simple scalar shifts on PPC64 expect a shift count that fits in 5 bits for 32-bit values or 6 bit for 64-bit values. If the shift count is a constant value greater than the max then the assembler sets it to the max for that size (31 for 32 bit values, 63 for 64 bit values). If the shift count is in a register, then
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 11.3K bytes - Viewed (0) -
src/compress/flate/testdata/huffman-shifts.dyn.expect
Klaus Post <******@****.***> 1457448890 +0100
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 11 17:40:52 UTC 2016 - 32 bytes - Viewed (0) -
src/math/fma.go
sign = uint32(b >> 63) exp = int32(b>>52) & mask mantissa = b & fracMask if exp == 0 { // Normalize value if subnormal. shift := uint(bits.LeadingZeros64(mantissa) - 11) mantissa <<= shift exp = 1 - int32(shift) } else { // Add implicit 1 bit mantissa |= 1 << 52 } return } // FMA returns x * y + z, computed with only one rounding.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jul 05 22:05:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/cmd/compile/internal/test/shift_test.go
if one16<<N<<N == 1 { t.Errorf("shift overflow mishandled") } if one16>>N>>N == 1 { t.Errorf("shift overflow mishandled") } if one16u>>N>>N == 1 { t.Errorf("shift overflow mishandled") } if one8<<N<<N == 1 { t.Errorf("shift overflow mishandled") } if one8>>N>>N == 1 { t.Errorf("shift overflow mishandled") } if one8u>>N>>N == 1 { t.Errorf("shift overflow mishandled") } }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Feb 23 22:26:39 UTC 2023 - 25.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 37.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/shift_test.go
Valu("c", OpConst64, c.config.Types.UInt64, amount, nil), Valu("shift", op, typ, 0, nil, "load", "c"), Valu("store", OpStore, types.TypeMem, 0, c.config.Types.UInt64, "resptr", "shift", "mem"), Exit("store"))) Compile(fun.f) return fun } func TestShiftToExtensionAMD64(t *testing.T) { c := testConfig(t) // Test that eligible pairs of constant shifts are converted to extensions. // For example:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 11 16:34:30 UTC 2022 - 4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "ANDshiftRAreg", argLength: 3, reg: gp31, asm: "AND"}, // arg0 & (arg1>>arg2), signed shift {name: "ORshiftLLreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1<<arg2 {name: "ORshiftRLreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1>>arg2, unsigned shift {name: "ORshiftRAreg", argLength: 3, reg: gp31, asm: "ORR"}, // arg0 | arg1>>arg2, signed shift
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0)