// TEQ
	TEQ	$255, R7             // ff0037e3
	TEQ	$4278190080, R9      // ff0439e3
	TEQ	R9<<30, R7           // 090f37e1
	TEQ	R9>>30, R7           // 290f37e1
	TEQ	R9->30, R7           // 490f37e1
	TEQ	R9@>30, R7           // 690f37e1
	TEQ	R9<<R8, R7           // 190837e1
	TEQ	R9>>R8, R7           // 390837e1
	TEQ	R9->R8, R7           // 590837e1
	TEQ	R9@>R8, R7           // 790837e1

(TST x (SRL y z)) => (TSTshiftRLreg x y z)
(TST x (SRA y z)) => (TSTshiftRAreg x y z)
(TEQ x (SLLconst [c] y)) => (TEQshiftLL x y [c])
(TEQ x (SRLconst [c] y)) => (TEQshiftRL x y [c])
(TEQ x (SRAconst [c] y)) => (TEQshiftRA x y [c])
(TEQ x (SLL y z)) => (TEQshiftLLreg x y z)
(TEQ x (SRL y z)) => (TEQshiftRLreg x y z)
(TEQ x (SRA y z)) => (TEQshiftRAreg x y z)
(CMN x (SLLconst [c] y)) => (CMNshiftLL x y [c])

	TEQ_EQ:            "TEQ.EQ",
	TEQ_NE:            "TEQ.NE",
	TEQ_CS:            "TEQ.CS",
	TEQ_CC:            "TEQ.CC",
	TEQ_MI:            "TEQ.MI",
	TEQ_PL:            "TEQ.PL",
	TEQ_VS:            "TEQ.VS",
	TEQ_VC:            "TEQ.VC",
	TEQ_HI:            "TEQ.HI",
	TEQ_LS:            "TEQ.LS",
	TEQ_GE:            "TEQ.GE",
	TEQ_LT:            "TEQ.LT",
	TEQ_GT:            "TEQ.GT",

	SUB.S	$7, Rs
	RSB 	$0, Rq, RM // M = -q
	MOVW.PL	Ra<<Rs, Rq

	// 1st Newton iteration
	MUL.PL	RM, Rq, Ra // a = -q*d
	BMI 	udiv_by_large_d
	MULAWT	Ra, Rq, Rq, Rq // q approx q-(q*q*d>>32)
	TEQ 	RM->1, RM // check for d=0 or d=1

	// 2nd Newton iteration
	MUL.NE	RM, Rq, Ra
	MOVW.NE	$0, Rs
	MULAL.NE Rq, Ra, (Rq,Rs)
	BEQ 	udiv_by_0_or_1

	// q now accurate enough for a remainder r, 0<=r<3*d

	// arm:`TST`,-`AND`
	// arm64:`TSTW`,-`AND`
	// 386:`TESTL`,-`ANDL`
	// amd64:`TESTL`,-`ANDL`
	c0 := a&b < 0
	// arm:`CMN`,-`ADD`
	// arm64:`CMNW`,-`ADD`
	c1 := a+b < 0
	// arm:`TEQ`,-`XOR`
	c2 := a^b < 0
	// arm64:`TST`,-`AND`
	// amd64:`TESTQ`,-`ANDQ`
	c3 := e&f < 0
	// arm64:`CMN`,-`ADD`
	c4 := e+f < 0
	// not optimized to single CMNW/CMN due to further use of b+d

		// remove the NOTUSETMP flag in optab.
		o1 = OP_SRR(c.opirr(-ASLLV), 0, p.From.Reg, p.To.Reg)
		o2 = OP_SRR(c.opirr(-ASRLV), 0, p.To.Reg, p.To.Reg)

	case 15: /* teq $c r,r */
		r := p.Reg
		if r == obj.REG_NONE {
			r = REGZERO
		}
		v := c.regoff(&p.From)
		/* only use 10 bits of trap code */
		o1 = OP_IRR(c.opirr(p.As), (uint32(v)&0x3FF)<<6, r, p.To.Reg)

		o2 = OP_16IRR(c.opirr(-ASRLV), uint32(32)&0x3f, uint32(p.To.Reg), uint32(p.To.Reg))

	case 15: // teq $c r,r
		v := c.regoff(&p.From)
		r := int(p.Reg)
		if r == 0 {
			r = REGZERO
		}
		/*
			teq c, r1, r2
			fallthrough
			==>
			bne r1, r2, 2
			break c
			fallthrough
		*/
		if p.As == ATEQ {

		break
	}
	// match: (TEQ x (SRL y z))
	// result: (TEQshiftRLreg x y z)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != OpARMSRL {
				continue
			}
			z := v_1.Args[1]
			y := v_1.Args[0]
			v.reset(OpARMTEQshiftRLreg)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	// match: (TEQ x (SRA y z))

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		argLen:  1,
		asm:     arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:        "TEQ",
		argLen:      2,
		commutative: true,
		asm:         arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14