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Results 11 - 20 of 89 for r2r1 (0.15 sec)
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src/runtime/sys_linux_arm64.s
MOVD RSP, R1 MOVD g_m(g), R21 // R21 = m // Set vdsoPC and vdsoSP for SIGPROF traceback. // Save the old values on stack and restore them on exit, // so this function is reentrant. MOVD m_vdsoPC(R21), R2 MOVD m_vdsoSP(R21), R3 MOVD R2, 8(RSP) MOVD R3, 16(RSP) MOVD $ret-8(FP), R2 // caller's SP MOVD LR, m_vdsoPC(R21) MOVD R2, m_vdsoSP(R21) MOVD m_curg(R21), R0 CMP g, R0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 24 18:53:44 UTC 2023 - 16.7K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
XOR R21,R24,R21 // xor done R24 MOVWZ (R10)(R8),R25 // tab[4][crc>>24] RLDICL $48,R7,$56,R24 // crc>>16&0xFF XOR R21,R25,R21 // xor done R25 ADD $1024,R10,R10 // &tab[5] SLD $2,R24,R24 // crc>>16&0xFF*4 MOVWZ (R10)(R24),R26 // tab[5][crc>>16&0xFF] XOR R21,R26,R21 // xor done R26 RLDICL $56,R7,$56,R25 // crc>>8 ADD $1024,R10,R10 // &tab[6] SLD $2,R25,R25 // crc>>8&FF*2 MOVBZ R7,R26 // crc&0xFF
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
loop: MOVD 8(R8), R20 // R20 = x[i] MOVD 16(R8), R21 // R21 = x[i+1] MOVD 24(R8), R22 // R22 = x[i+2] MOVDU 32(R8), R23 // R23 = x[i+3] MULLD R9, R20, R24 // R24 = z0[i] MULHDU R9, R20, R20 // R20 = z1[i] ADDC R4, R24 // R24 = z0[i] + c MULLD R9, R21, R25 MULHDU R9, R21, R21 ADDE R20, R25 MULLD R9, R22, R26 MULHDU R9, R22, R22
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
maven-compat/src/test/java/org/apache/maven/project/artifact/DefaultMavenMetadataCacheTest.java
// sanity checks assertNotSame(a1, a2); assertNotSame(lr1, lr2); assertNotSame(rr1, rr2); DefaultMavenMetadataCache.CacheKey k1 = new DefaultMavenMetadataCache.CacheKey(a1, false, lr1, Collections.singletonList(rr1)); DefaultMavenMetadataCache.CacheKey k2 = new DefaultMavenMetadataCache.CacheKey(a2, false, lr2, Collections.singletonList(rr2));
Registered: Wed Jun 12 09:55:16 UTC 2024 - Last Modified: Thu Apr 25 05:46:50 UTC 2024 - 3K bytes - Viewed (0) -
src/internal/bytealg/index_ppc64x.s
MOVD $2, R15 // Set up index // Set up masks for use with VSEL MOVD $0xff, R21 // Set up mask 0xff000000ff000000... SLD $24, R21 MTVSRD R21, V10 VSPLTW $1, V10, V29 VSLDOI $2, V29, V29, V30 // Mask 0x0000ff000000ff00... MOVD $0xffff, R21 SLD $16, R21 MTVSRD R21, V10 VSPLTW $1, V10, V31 // Mask 0xffff0000ffff0000... VSPLTW $0, V0, V1 // Splat 1st word of separator
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 16:47:45 UTC 2023 - 31.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// } SLL $19, R22, R21 // 0016acc0 SLLV $19, R22, R21 // 0016acf8 SRL $31, R6, R17 // 00068fc2 SRLV $31, R6, R17 // 00068ffa SRA $8, R8, R19 // 00089a03 SRAV $19, R8, R7 // 00083cfb ROTR $12, R8, R3 // 00281b02 ROTRV $8, R22, R22 // 0036b23a // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $19, R21 // 0015acc0 SLLV $19, R21 // 0015acf8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/crypto/internal/edwards25519/field/fe_arm64.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 1K bytes - Viewed (0) -
src/runtime/preempt_arm64.s
STP (R4, R5), 40(RSP) STP (R6, R7), 56(RSP) STP (R8, R9), 72(RSP) STP (R10, R11), 88(RSP) STP (R12, R13), 104(RSP) STP (R14, R15), 120(RSP) STP (R16, R17), 136(RSP) STP (R19, R20), 152(RSP) STP (R21, R22), 168(RSP) STP (R23, R24), 184(RSP) STP (R25, R26), 200(RSP) MOVD NZCV, R0 MOVD R0, 216(RSP) MOVD FPSR, R0 MOVD R0, 224(RSP) FSTPD (F0, F1), 232(RSP) FSTPD (F2, F3), 248(RSP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 03 01:58:56 UTC 2022 - 2K bytes - Viewed (0) -
src/math/big/arith_arm64.s
LSL R4, R6, R20 LSR R3, R6 ORR R8, R20 LSL R4, R7, R21 LSR R3, R7, R8 ORR R6, R21 STP.P (R20, R21), 16(R0) SUB $2, R1 loop: CBZ R1, done LDP.P 32(R2), (R10, R11) LDP -16(R2), (R12, R13) LSL R4, R10, R20 LSR R3, R10 ORR R8, R20 // z[i] = (x[i] >> s) | (x[i+1] << (64 - s)) LSL R4, R11, R21 LSR R3, R11 ORR R10, R21 LSL R4, R12, R22 LSR R3, R12 ORR R11, R22
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 11.8K bytes - Viewed (0) -
src/runtime/cgo/abi_arm64.h
#define SAVE_R19_TO_R28(offset) \ STP (R19, R20), ((offset)+0*8)(RSP) \ STP (R21, R22), ((offset)+2*8)(RSP) \ STP (R23, R24), ((offset)+4*8)(RSP) \ STP (R25, R26), ((offset)+6*8)(RSP) \ STP (R27, g), ((offset)+8*8)(RSP) #define RESTORE_R19_TO_R28(offset) \ LDP ((offset)+0*8)(RSP), (R19, R20) \ LDP ((offset)+2*8)(RSP), (R21, R22) \ LDP ((offset)+4*8)(RSP), (R23, R24) \ LDP ((offset)+6*8)(RSP), (R25, R26) \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 30 01:28:43 UTC 2022 - 1.5K bytes - Viewed (0)