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Results 11 - 16 of 16 for mtvsrdd (0.14 sec)
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src/cmd/compile/internal/ssa/_gen/PPC64.rules
(MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr x _)) => (MFVSRD x) (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr x _)) => (MTVSRD x) (FMOVDstore [off] {sym} ptr (MTVSRD x) mem) => (MOVDstore [off] {sym} ptr x mem) (MOVDstore [off] {sym} ptr (MFVSRD x) mem) => (FMOVDstore [off] {sym} ptr x mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/math/big/arith_ppc64x.s
CMP R8, R4 BGE loopexit // Already at end? // vectorize if len(z) is >=3, else jump to scalar loop CMP R4, $3 BLT scalar MTVSRD R9, VS38 // s VSPLTB $7, V6, V4 MTVSRD R5, VS39 // ŝ VSPLTB $7, V7, V2 ADD $-2, R4, R16 PCALIGN $16 loopback: ADD $-1, R8, R10 SLD $3, R10 LXVD2X (R6)(R10), VS32 // load x[i-1], x[i]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 16.8K bytes - Viewed (0) -
src/hash/crc32/crc32_ppc64le.s
NOR R3,R3,R3 // ^crc MOVWZ R3,R3 // 32 bits VXOR zeroes,zeroes,zeroes // clear the V reg VSPLTISW $-1,V0 VSLDOI $4,V29,V0,mask_32bit VSLDOI $8,V29,V0,mask_64bit VXOR V8,V8,V8 MTVSRD R3,VS40 // crc initial value VS40 = V8 #ifdef REFLECT VSLDOI $8,zeroes,V8,V8 // or: VSLDOI V29,V8,V27,4 for top 32 bits? #else VSLDOI $4,V8,zeroes,V8 #endif #ifdef BYTESWAP_DATA
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 06 12:09:50 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
// the word-load instructions. (Xi2f64 (MOVDload ptr )) can be (FMOVDload ptr) {name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"}, // move 64 bits of F register into G register {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"}, // move 64 bits of G register into F register
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
// result: (MFVSRD (FCTIWZ x)) for { x := v_0 v.reset(OpPPC64MFVSRD) v0 := b.NewValue0(v.Pos, OpPPC64FCTIWZ, typ.Float64) v0.AddArg(x) v.AddArg(v0) return true } } func rewriteValuePPC64_OpCvt64Fto64(v *Value) bool { v_0 := v.Args[0] b := v.Block typ := &b.Func.Config.Types // match: (Cvt64Fto64 x) // result: (MFVSRD (FCTIDZ x)) for { x := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
outputs: []outputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 }, }, }, { name: "MTVSRD", argLen: 1, asm: ppc64.AMTVSRD, reg: regInfo{ inputs: []inputInfo{ {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 },
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)