)

	var S390Xops = []opData{
		// fp ops
		{name: "FADDS", argLength: 2, reg: fp21clobber, typ: "(Float32,Flags)", asm: "FADDS", commutative: true, resultInArg0: true}, // fp32 arg0 + arg1
		{name: "FADD", argLength: 2, reg: fp21clobber, typ: "(Float64,Flags)", asm: "FADD", commutative: true, resultInArg0: true},   // fp64 arg0 + arg1

		{name: "UMODW", argLength: 2, reg: gp21, asm: "UREMW"},                                                        // arg0 % arg1, unsigned, 32 bit

		{name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true},   // arg0 + arg1
		{name: "FADDD", argLength: 2, reg: fp21, asm: "FADDD", commutative: true},   // arg0 + arg1
		{name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"},                      // arg0 - arg1

	ADDSW R12.SXTX<<1, R29, R7                 // a7e72c2b
	ADDS R24.UXTX<<4, R25, R21                 // 357338ab
	ADDSW $(3525<<12), R3, R11                 // ADDSW $14438400, R3, R11          // 6b147731
	ADDS $(3525<<12), R3, R11                  // ADDS $14438400, R3, R11           // 6b1477b1
	ADDSW R7->22, R14, R13                     // cd59872b
	ADDS R14>>7, ZR, R4                        // e41f4eab

	EXTSWCC:        "extsw.",
	FADDS:          "fadds",
	FADDSCC:        "fadds.",
	FCFID:          "fcfid",
	FCFIDCC:        "fcfid.",
	FCTID:          "fctid",
	FCTIDCC:        "fctid.",
	FCTIDZ:         "fctidz",
	FCTIDZCC:       "fctidz.",
	FDIVS:          "fdivs",
	FDIVSCC:        "fdivs.",
	FMADDS:         "fmadds",
	FMADDSCC:       "fmadds.",
	FMSUBS:         "fmsubs",

(Select0 (F(ADDS|SUBS) (FMULS y z) x)) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)

// Convert floating point comparisons against zero into 'load and test' instructions.
(F(CMP|CMPS) x (FMOV(D|S)const [0.0])) => (LT(D|E)BR x)
(F(CMP|CMPS) (FMOV(D|S)const [0.0]) x) => (InvertFlags (LT(D|E)BR <v.Type> x))

// FSUB, FSUBS, FADD, FADDS now produce a condition code representing the

(FNEGS  (FNMULS x y)) => (FMULS  x y)
(FNEGD  (FNMULD x y)) => (FMULD  x y)
(FNMULS (FNEGS  x) y) => (FMULS  x y)
(FNMULD (FNEGD  x) y) => (FMULD  x y)

(FADDS a (FMULS  x y)) && a.Block.Func.useFMA(v) => (FMADDS  a x y)
(FADDD a (FMULD  x y)) && a.Block.Func.useFMA(v) => (FMADDD  a x y)
(FSUBS a (FMULS  x y)) && a.Block.Func.useFMA(v) => (FMSUBS  a x y)
(FSUBD a (FMULD  x y)) && a.Block.Func.useFMA(v) => (FMSUBD  a x y)

//
(Add(Ptr|64|32|16|8) ...) => (ADD ...)
(Add64F ...) => (FADD ...)
(Add32F ...) => (FADDS ...)

(Sub(Ptr|64|32|16|8) ...) => (SUB ...)
(Sub32F ...) => (FSUBS ...)
(Sub64F ...) => (FSUB ...)

(Min(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMINJDP x y)
(Max(32|64)F x y) && buildcfg.GOPPC64 >= 9 => (XSMAXJDP x y)

// Combine 64 bit integer multiply and adds

	FNMADDD	F1, F3, F2, F4                  // 440c611f
	FNMSUBS	F1, F3, F2, F4                  // 448c211f
	FNMSUBD	F1, F3, F2, F4                  // 448c611f
	FADDS	F2, F3, F4                      // 6428221e
	FADDD	F1, F2                          // 4228611e
	VDUP	V19.S[0], V17.S4                // 7106044e
	VTRN1	V3.D2, V2.D2, V20.D2            // 5428c34e
	VTRN2	V3.D2, V2.D2, V21.D2            // 5568c34e

	b0[idx] = b1
}

// ----------- //
//    Fused    //
// ----------- //

func FusedAdd32(x, y, z float32) float32 {
	// s390x:"FMADDS\t"
	// ppc64x:"FMADDS\t"
	// arm64:"FMADDS"
	// riscv64:"FMADDS\t"
	return x*y + z
}

func FusedSub32_a(x, y, z float32) float32 {
	// s390x:"FMSUBS\t"
	// ppc64x:"FMSUBS\t"
	// riscv64:"FMSUBS\t"
	return x*y - z
}

		y := v_0_0.Args[0]
		if !(x.Block.Func.useFMA(v)) {
			break
		}
		v.reset(OpS390XFMSUB)
		v.AddArg3(x, y, z)
		return true
	}
	// match: (Select0 (FADDS (FMULS y z) x))
	// cond: x.Block.Func.useFMA(v)
	// result: (FMADDS x y z)
	for {
		if v_0.Op != OpS390XFADDS {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]