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Results 11 - 20 of 180 for destruction (0.19 sec)

  1. src/cmd/asm/internal/asm/line_test.go

    		{"VADDPD.RZ_SAE.SAE X0, X1, X2", `bad suffix combination`},
    
    		// BSWAP on 16-bit registers is undefined. See #29167,
    		{"BSWAPW DX", `unrecognized instruction`},
    		{"BSWAPW R11", `unrecognized instruction`},
    	})
    }
    
    func testBadInstParser(t *testing.T, goarch string, tests []badInstTest) {
    	for i, test := range tests {
    		arch, ctxt := setArch(goarch)
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 29 07:48:38 UTC 2023
    - 1.9K bytes
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  2. licenses/github.com/shopspring/decimal/LICENSE

    Copyright (c) 2015 Spring, Inc.
    
    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to deal
    in the Software without restriction, including without limitation the rights
    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    copies of the Software, and to permit persons to whom the Software is
    Registered: Wed Nov 06 22:53:10 UTC 2024
    - Last Modified: Wed Jan 06 22:59:30 UTC 2021
    - 2.2K bytes
    - Viewed (0)
  3. doc/asm.html

    Instead, the compiler operates on a kind of semi-abstract instruction set,
    and instruction selection occurs partly after code generation.
    The assembler works on the semi-abstract form, so
    when you see an instruction like <code>MOV</code>
    what the toolchain actually generates for that operation might
    not be a move instruction at all, perhaps a clear or load.
    Or it might correspond exactly to the machine instruction with that name.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/asm.go

    		}
    		p.errorf("wrong number of arguments to %s instruction", op)
    		return
    	case 4:
    		if p.arch.Family == sys.S390X || p.arch.Family == sys.PPC64 {
    			// 4-operand compare-and-branch.
    			prog.From = a[0]
    			prog.Reg = p.getRegister(prog, op, &a[1])
    			prog.AddRestSource(a[2])
    			target = &a[3]
    			break
    		}
    		p.errorf("wrong number of arguments to %s instruction", op)
    		return
    	default:
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Mon Oct 21 14:11:44 UTC 2024
    - 25.5K bytes
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  5. src/cmd/asm/internal/asm/testdata/amd64.s

    // Copyright 2015 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    // This input was created by taking the instruction productions in
    // the old assembler's (6a's) grammar and hand-writing complete
    // instructions for each rule, to guarantee we cover the same space.
    
    #include "../../../../../runtime/textflag.h"
    
    TEXT	foo(SB), DUPOK|NOSPLIT, $0
    
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Apr 09 18:57:21 UTC 2019
    - 3.3K bytes
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  6. src/cmd/asm/internal/arch/arch.go

    const (
    	RFP = -(iota + 1)
    	RSB
    	RSP
    	RPC
    )
    
    // Arch wraps the link architecture object with more architecture-specific information.
    type Arch struct {
    	*obj.LinkArch
    	// Map of instruction names to enumeration.
    	Instructions map[string]obj.As
    	// Map of register names to enumeration.
    	Register map[string]int16
    	// Table of register prefix names. These are things like R for R(0) and SPR for SPR(268).
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Oct 24 12:32:56 UTC 2024
    - 21.5K bytes
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  7. src/cmd/asm/internal/arch/riscv64.go

    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    // This file encapsulates some of the odd characteristics of the RISCV64
    // instruction set, to minimize its interaction with the core of the
    // assembler.
    
    package arch
    
    import (
    	"cmd/internal/obj"
    	"cmd/internal/obj/riscv"
    )
    
    // IsRISCV64AMO reports whether the op (as defined by a riscv.A*
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Sun Mar 15 08:13:28 UTC 2020
    - 943 bytes
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  8. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	MOVWU	X5, (X6)			// ERROR "unsupported unsigned store"
    	MOVF	F0, F1, F2			// ERROR "illegal MOV instruction"
    	MOVD	F0, F1, F2			// ERROR "illegal MOV instruction"
    	MOV	X10, X11, X12			// ERROR "illegal MOV instruction"
    	MOVW	X10, X11, X12			// ERROR "illegal MOV instruction"
    	RORI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 2.8K bytes
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  9. apache-maven/src/main/appended-resources/licenses/MIT.txt

     Copyright <YEAR> <COPYRIGHT HOLDER>
    
     Permission is hereby granted, free  of charge, to any person obtaining
     a  copy  of this  software  and  associated  documentation files  (the
     "Software"), to  deal in  the Software without  restriction, including
     without limitation  the rights to  use, copy, modify,  merge, publish,
     distribute,  sublicense, and/or sell  copies of  the Software,  and to
     permit persons to whom the Software  is furnished to do so, subject to
    Registered: Sun Nov 03 03:35:11 UTC 2024
    - Last Modified: Fri May 17 19:14:22 UTC 2024
    - 1.1K bytes
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  10. licenses/github.com/BurntSushi/toml/cmd/toml-test-decoder/COPYING

    Copyright (c) 2013 TOML authors
    
    Permission is hereby granted, free of charge, to any person obtaining a copy
    of this software and associated documentation files (the "Software"), to deal
    in the Software without restriction, including without limitation the rights
    to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    copies of the Software, and to permit persons to whom the Software is
    Registered: Wed Nov 06 22:53:10 UTC 2024
    - Last Modified: Mon Oct 28 19:33:59 UTC 2019
    - 1.1K bytes
    - Viewed (0)
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