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tensorflow/compiler/mlir/tensorflow/tests/convert-tf-control-flow-to-scf.mlir
// CHECK-NEXT: scf.condition(%[[CONDITION]]) %[[ARG3]], %[[ARG4]] : tensor<f32>, tensor<*xf32> // CHECK-NEXT: } do { // CHECK-NEXT: ^bb0(%[[ARG3]]: tensor<f32>, %[[ARG4]]: tensor<*xf32>): // CHECK-NEXT: %[[SUB:.*]] = "tf.Sub"(%[[ARG3]], %[[CST]]) : (tensor<f32>, tensor<f32>) -> tensor<f32> // CHECK-NEXT: scf.yield %[[SUB]], %[[ARG4]] : tensor<f32>, tensor<*xf32> // CHECK-NEXT: }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 5.2K bytes - Viewed (0) -
platforms/software/dependency-management/src/test/groovy/org/gradle/internal/component/model/DefaultIvyArtifactNameTest.groovy
getExtension() >> "art-ext" getType() >> "art-type" getClassifier() >> "art-classifier" } when: 1 * publishArtifact.getName() >> "art-name" then: def name = DefaultIvyArtifactName.forPublishArtifact(publishArtifact) name.name == "art-name" name.extension == "art-ext" name.type == "art-type"
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Tue Nov 07 18:43:39 UTC 2023 - 2.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/tests/tfl_legalize_hlo.mlir
%6 = mhlo.compare GE, %arg1, %arg3 : (tensor<i32>, tensor<i32>) -> tensor<i1> %7 = mhlo.select %6, %arg1, %arg3 : tensor<i1>, tensor<i32> %8 = mhlo.compare EQ, %arg1, %arg3 : (tensor<i32>, tensor<i32>) -> tensor<i1> %9 = mhlo.minimum %arg2, %arg4 : tensor<i32> %10 = mhlo.select %6, %arg2, %arg4 : tensor<i1>, tensor<i32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 40.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tpu_parallel_execute_sink_resource_write.mlir
// CHECK-SAME: ([[ARG0:%.+]]: tensor<i1>, [[ARG1:%.+]]: tensor<i32>, [[ARG2:%.+]]: tensor<i64>, [[ARG3:%.+]]: tensor<f32>, [[ARG4:%.+]]: tensor<f64>, [[ARG5:%.+]]: tensor<!tf_type.resource>, [[ARG6:%.+]]: tensor<!tf_type.resource>) func.func @replace_multiple_outputs(%arg0: tensor<i1>, %arg1: tensor<i32>, %arg2: tensor<i64>, %arg3: tensor<f32>, %arg4: tensor<f64>, %arg5: tensor<!tf_type.resource>, %arg6: tensor<!tf_type.resource>) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Mar 28 12:06:33 UTC 2022 - 7.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/lstm.mlir
// Ensure lstm roundtrip exactly
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 20.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tpu_update_embedding_enqueue_op_inputs.mlir
// CHECK-SAME: %[[ARG_7:[a-z0-9]*]]: tensor<!tf_type.string> func.func @check_enqueue_ops_update_for_eval(%arg0: tensor<?x2xi32>, %arg1: tensor<?x2xi32>, %arg2 :tensor<?x2xi32>, %arg3: tensor<?xi32>, %arg4: tensor<?xi32>, %arg5: tensor<?xi32>, %arg6: tensor<!tf_type.string>, %arg7: tensor<!tf_type.string>) -> () { // CHECK: %[[CONST_0:.*]] = "tf.Const"() %0 = "tf.Const"() {value = dense<[]> : tensor<0xf32>} : () -> tensor<0xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 5.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/prepare-tf-with-allowing-bf16-and-f16-type-legalization.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 26 23:53:32 UTC 2022 - 2.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_weights.mlir
// CHECK: %[[MATMUL_1:.*]] = "tf.MatMul"(%arg3, %arg4) <{transpose_a = false, transpose_b = false}> {device = ""} : (tensor<1x1024xf32>, tensor<1024x1024xf32>) -> tensor<1x1024xf32> // CHECK: %[[IDENTITY:.*]] = "tf.Identity"(%arg4) {device = ""} : (tensor<1024x1024xf32>) -> tensor<1024x1024xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 42K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/basic_lstm.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 1.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir
%9 = "tf.Conv2D"(%8, %arg4) { data_format = "NCHW", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 1, 1] } : (tensor<?x64x56x56xf32>, tensor<1x1x64x256xf32>) -> tensor<?x256x56x56xf32> // CHECK: %[[CONV1:[0-9]*]] = "tf.Conv2D"(%[[MAX_POOL]], %arg4) // CHECK-SAME: data_format = "NHWC"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 7.3K bytes - Viewed (0)