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Results 11 - 20 of 24 for absIdx (0.15 sec)
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src/regexp/all_test.go
// of a character. {"[a-c]*", "x", "\u65e5", "x\u65e5x"}, {"[^\u65e5]", "x", "abc\u65e5def", "xxx\u65e5xxx"}, // Start and end of a string. {"^[a-c]*", "x", "abcdabc", "xdabc"}, {"[a-c]*$", "x", "abcdabc", "abcdx"}, {"^[a-c]*$", "x", "abcdabc", "abcdabc"}, {"^[a-c]*", "x", "abc", "x"}, {"[a-c]*$", "x", "abc", "x"}, {"^[a-c]*$", "x", "abc", "x"}, {"^[a-c]*", "x", "dabce", "xdabce"}, {"[a-c]*$", "x", "dabce", "dabcex"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:36:03 UTC 2024 - 25.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MOVDF F4, F5 // 85181901 MOVWF F4, F5 // 85101d01 MOVFW F4, F5 // 85041b01 MOVWD F4, F5 // 85201d01 MOVDW F4, F5 // 85081b01 NEGF F4, F5 // 85141401 NEGD F4, F5 // 85181401 ABSD F4, F5 // 85081401 TRUNCDW F4, F5 // 85881a01 TRUNCFW F4, F5 // 85841a01 SQRTF F4, F5 // 85441401 SQRTD F4, F5 // 85481401 DBAR // 00007238 NOOP // 00004003
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armerror.s
FNMULSF F0, F1 // ERROR "illegal combination" NEGF F0, F1, F2 // ERROR "illegal combination" NEGD F0, F1, F2 // ERROR "illegal combination" ABSF F0, F1, F2 // ERROR "illegal combination" ABSD F0, F1, F2 // ERROR "illegal combination" SQRTF F0, F1, F2 // ERROR "illegal combination" SQRTD F0, F1, F2 // ERROR "illegal combination" MOVF F0, F1, F2 // ERROR "illegal combination"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 03 14:06:21 UTC 2017 - 14.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// // LBRA rel label4: BFPT 1(PC) BFPT label4 // BFPT 87 // // floating point operate // // LFCONV freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ABSD F1, F2 // LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 // shifts
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 // shifts
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// } MOVW $1, R1 MOVW $foo(SB), R1 MOVV $1, R1 MOVV $foo(SB), R1 // // floating point operate // // LFCONV freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ABSD F1, F2 // LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"}, {VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"}, {VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"}, {VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"}, {VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"}, {VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"}, {VSQRT_EQ_F64, []int{1, 0}, "VSQRT", "SQRTD"}, {VCMP_EQ_F32, []int{1, 0}, "VCMP", "CMPF"}, {VCMP_EQ_F64, []int{1, 0}, "VCMP", "CMPD"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64 {name: "CLZ", argLength: 1, reg: gp11, asm: "CLZ"}, // count leading zero {name: "REV", argLength: 1, reg: gp11, asm: "REV"}, // reverse byte order
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
(Mod8 x y) => (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y))) (Mod8u x y) => (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))) // math package intrinsics (Abs ...) => (ABSD ...) // (x + y) / 2 with x>=y becomes (x - y) / 2 + y (Avg32u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y) (And(32|16|8) ...) => (AND ...) (Or(32|16|8) ...) => (OR ...) (Xor(32|16|8) ...) => (XOR ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0)