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Results 11 - 16 of 16 for V31 (0.03 sec)
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compat/maven-model-builder/src/main/java/org/apache/maven/model/validation/DefaultModelValidator.java
addViolation( problems, Severity.WARNING, Version.V31, prefix + prefix2 + "scope", key, "declares usage of deprecated 'system' scope ", dependency);
Registered: Sun Dec 28 03:35:09 UTC 2025 - Last Modified: Wed Sep 03 15:06:05 UTC 2025 - 66.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
MFVSRD VS1, R3 // 7c230066 MTFPRD R3, F0 // 7c030166 MFVRD V0, R3 // 7c030067 MFVSRLD VS63,R4 // 7fe40267 MFVSRLD V31,R4 // 7fe40267 MFVSRWZ VS33,R4 // 7c2400e7 MFVSRWZ V1,R4 // 7c2400e7 MTVSRD R3, VS1 // 7c230166 MTVSRDD R3, R4, VS1 // 7c232366
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 21 18:27:17 UTC 2024 - 51.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
// registers in []. There may be comma-separated ranges or individual // registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4]. // For ARM, only R0 through R15 may appear. // For ARM64, V0 through V31 with arrangement may appear. // // For 386/AMD64 register list specifies 4VNNIW-style multi-source operand. // For range of 4 elements, Intel manual uses "+3" notation, for example: //
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Nov 12 03:59:40 UTC 2025 - 37.3K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
INV V1 // The following macros are used for // the stitched implementation within // counterCryptASM. // Load the initial GCM counter value // in V30 and set up the counter increment // in V31 #define SETUP_COUNTER \ P8_LXVB16X(COUNTER, R0, V30); \ VSPLTISB $1, V28; \ VXOR V31, V31, V31; \ VSLDOI $1, V31, V28, V31 // These macros set up the initial value // for a single encryption, or 4 or 8 // stitched encryptions implemented // with interleaving vciphers. // // The input value for each encryption...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
VMOVQ V7.BU[0], R4 // e480f372 VMOVQ V7.BU[1], R4 // e484f372 VMOVQ V9.BU[3], R5 // 258df372 VMOVQ V10.HU[2], R6 // 46c9f372 VMOVQ V11.WU[2], R7 // 67e9f372 VMOVQ V31.VU[1], R8 // e8f7f372 XVMOVQ X1.W[2], R7 // 27c8ef76 XVMOVQ X6.V[2], R8 // c8e8ef76 XVMOVQ X8.WU[2], R7 // 07c9f376 XVMOVQ X31.VU[2], R8 // e8ebf376
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 27 00:46:52 UTC 2025 - 44.5K bytes - Viewed (0) -
lib/fips140/v1.0.0-c2097c7c.zip
INV V1 // The following macros are used for // the stitched implementation within // counterCryptASM. // Load the initial GCM counter value // in V30 and set up the counter increment // in V31 #define SETUP_COUNTER \ P8_LXVB16X(COUNTER, R0, V30); \ VSPLTISB $1, V28; \ VXOR V31, V31, V31; \ VSLDOI $1, V31, V28, V31 // These macros set up the initial value // for a single encryption, or 4 or 8 // stitched encryptions implemented // with interleaving vciphers. // // The input value for each encryption...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Sep 25 19:53:19 UTC 2025 - 642.7K bytes - Viewed (0)