SuffixLoop:
	for i, a := range inst.Args {
		if a == nil {
			break
		}
		switch a := a.(type) {
		case Reg:
			switch inst.Op {
			case MOVSX, MOVZX:
				continue

			case SHL, SHR, RCL, RCR, ROL, ROR, SAR:
				if i == 1 {
					// shift count does not tell us operand size
					continue
				}

			case CRC32:
				// The source argument does tell us operand size,

// Some macros

// ROL rotates the uint32s in register R left by N bits, using temporary T.
#define ROL(N, R, T) \
	MOVO R, T; PSLLL $(N), T; PSRLL $(32-(N)), R; PXOR T, R

// ROL16 rotates the uint32s in register R left by 16, using temporary T if needed.
#ifdef GOAMD64_v2
#define ROL16(R, T) PSHUFB ·rol16<>(SB), R
#else
#define ROL16(R, T) ROL(16, R, T)
#endif

	if buildcfg.GORISCV64 >= 22 {
		// Rotation instructions are supported natively.
		return []*instruction{ins}
	}

	switch ins.as {
	case AROL, AROLW, AROR, ARORW:
		// ROL -> OR (SLL x y) (SRL x (NEG y))
		// ROR -> OR (SRL x y) (SLL x (NEG y))
		sllOp, srlOp := ASLL, ASRL
		if ins.as == AROLW || ins.as == ARORW {
			sllOp, srlOp = ASLLW, ASRLW
		}
		shift1, shift2 := sllOp, srlOp

	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ROL x (MOVDconst [val]))
	// result: (RORI [int64(int8(-val)&63)] x)
	for {
		x := v_0
		if v_1.Op != OpRISCV64MOVDconst {
			break
		}
		val := auxIntToInt64(v_1.AuxInt)
		v.reset(OpRISCV64RORI)
		v.AuxInt = int64ToAuxInt(int64(int8(-val) & 63))
		v.AddArg(x)
		return true
	}
	// match: (ROL x (NEG y))
	// result: (ROR x y)
	for {

1C38..1C3A    ; disallowed                             # NA   <reserved-1C38>..<reserved-1C3A>
1C3B..1C3F    ; valid                  ;      ; NV8    # 5.1  LEPCHA PUNCTUATION TA-ROL..LEPCHA PUNCTUATION TSHOOK
1C40..1C49    ; valid                                  # 5.1  LEPCHA DIGIT ZERO..LEPCHA DIGIT NINE
1C4A..1C4C    ; disallowed                             # NA   <reserved-1C4A>..<reserved-1C4C>

			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "ROL",
		argLen: 2,
		asm:    riscv.AROL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30