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Results 11 - 17 of 17 for XORL (0.07 sec)
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src/runtime/sys_windows_amd64.s
LEAQ m_tls(CX), DI MOVQ CX, g_m(DX) MOVQ DX, g(DI) CALL runtime·settls(SB) // clobbers CX CALL runtime·stackcheck(SB) // clobbers AX,CX CALL runtime·mstart(SB) POP_REGS_HOST_TO_ABI0() XORL AX, AX // return 0 == success RET // set tls base to DI TEXT runtime·settls(SB),NOSPLIT,$0 MOVQ runtime·tls_g(SB), CX MOVQ DI, 0(CX)(GS) RET TEXT runtime·nanotime1(SB),NOSPLIT,$0-8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Feb 19 07:24:08 UTC 2024 - 8.4K bytes - Viewed (0) -
src/crypto/aes/gcm_amd64.s
#define ptx SI #define ks AX #define tPtr R8 #define ptxLen R9 #define aluCTR R10 #define aluTMP R11 #define aluK R12 #define NR R13 #define increment(i) ADDL $1, aluCTR; MOVL aluCTR, aluTMP; XORL aluK, aluTMP; BSWAPL aluTMP; MOVL aluTMP, (3*4 + 8*16 + i*16)(SP) #define aesRnd(k) AESENC k, B0; AESENC k, B1; AESENC k, B2; AESENC k, B3; AESENC k, B4; AESENC k, B5; AESENC k, B6; AESENC k, B7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 23.4K bytes - Viewed (0) -
src/runtime/asm_386.s
MOVL SP, (g_stack+stack_hi)(BP) // find out information about the processor we're on // first see if CPUID instruction is supported. PUSHFL PUSHFL XORL $(1<<21), 0(SP) // flip ID bit POPFL PUSHFL POPL AX XORL 0(SP), AX POPFL // restore EFLAGS TESTL $(1<<21), AX JNE has_cpuid bad_proc: // show that the program requires MMX. MOVL $2, 0(SP) MOVL $bad_proc_msg<>(SB), 4(SP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 15 15:45:13 UTC 2024 - 43.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(ORQ x (MOVQconst [c])) && is32Bit(c) => (ORQconst [int32(c)] x) (ORQ x (MOVLconst [c])) => (ORQconst [c] x) (ORL x (MOVLconst [c])) => (ORLconst [c] x) (XORQ x (MOVQconst [c])) && is32Bit(c) => (XORQconst [int32(c)] x) (XORL x (MOVLconst [c])) => (XORLconst [c] x) (SHLQ x (MOV(Q|L)const [c])) => (SHLQconst [int8(c&63)] x) (SHLL x (MOV(Q|L)const [c])) => (SHLLconst [int8(c&31)] x) (SHRQ x (MOV(Q|L)const [c])) => (SHRQconst [int8(c&63)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/runtime/asm_amd64.s
#endif #ifdef NEED_EXT_FEATURES_CX MOVL $0x80000001, AX CPUID ANDL $NEED_EXT_FEATURES_CX, CX CMPL CX, $NEED_EXT_FEATURES_CX JNE bad_cpu #endif #ifdef NEED_OS_SUPPORT_AX XORL CX, CX XGETBV ANDL $NEED_OS_SUPPORT_AX, AX CMPL AX, $NEED_OS_SUPPORT_AX JNE bad_cpu #endif #ifdef NEED_DARWIN_SUPPORT MOVQ $commpage64_version, BX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v.AddArg(x) return true } break } // match: (XORL x x) // result: (MOVLconst [0]) for { x := v_0 if x != v_1 { break } v.reset(OpAMD64MOVLconst) v.AuxInt = int32ToAuxInt(0) return true } // match: (XORL x l:(MOVLload [off] {sym} ptr mem)) // cond: canMergeLoadClobber(v, l, x) && clobber(l)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "XORL", argLen: 2, commutative: true, resultInArg0: true, clobberFlags: true, asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)