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Results 11 - 15 of 15 for ANDS (0.04 sec)
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src/cmd/asm/internal/asm/parse.go
var op int16 switch p.next().ScanToken { case lex.LSH: op = 0 case lex.RSH: op = 1 case lex.ARR: op = 2 case lex.ROT: // following instructions on ARM64 support rotate right // AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN op = 3 } tok := p.next() str := tok.String() var count int16 switch tok.ScanToken { case scanner.Ident: if p.arch.Family == sys.ARM64 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Feb 21 14:34:57 UTC 2024 - 36.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem) // fold extensions and ANDs together (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x) (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x) (MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
(ANDQ (MOVQconst [c]) x) && isUint64PowerOfTwo(^c) && uint64(^c) >= 1<<31 => (BTRQconst [int8(log64(^c))] x) // Special-case bit patterns on first/last bit. // generic.rules changes ANDs of high-part/low-part masks into a couple of shifts, // for instance: // x & 0xFFFF0000 -> (x >> 16) << 16 // x & 0x80000000 -> (x >> 31) << 31 //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(MOVHreg x:(MOVBUload _ _)) => (MOVWreg x) (MOVHreg x:(MOVHload _ _)) => (MOVWreg x) (MOVHUreg x:(MOVBUload _ _)) => (MOVWreg x) (MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x) // fold extensions and ANDs together (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x) (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x) (MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
(Less16 (Const16 <t> [math.MaxInt16-1]) x) => (Eq16 x (Const16 <t> [math.MaxInt16])) (Less8 (Const8 <t> [math.MaxInt8 -1]) x) => (Eq8 x (Const8 <t> [math.MaxInt8 ])) // Ands clear bits. Ors set bits. // If a subsequent Or will set all the bits // that an And cleared, we can skip the And. // This happens in bitmasking code like: // x &^= 3 << shift // clear two old bits
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0)