VSHASIGMAD	$15, e, $1, S1; \
	VADDUDM		xi, h, h; \
	VSHASIGMAD	$0, a, $1, S0; \
	VSHASIGMAD	$15, xj_14, $0, s1; \
	VADDUDM		FUNC, h, h; \
	VXOR		b, a, FUNC; \
	VADDUDM		xj_9, xj, xj; \
	VADDUDM		S1, h, h; \
	VSEL		b, c, FUNC, FUNC; \
	VADDUDM		KI, g, g; \
	VADDUDM		h, d, d; \
	VADDUDM		FUNC, S0, S0; \
	VADDUDM		s0, xj, xj; \
	LVX		(TBL)(idx), KI; \
	VADDUDM		S0, h, h; \
	VADDUDM		s1, xj, xj

	VCMPEQUB V0, V1, V0
	VPOPCNTD V2, V2		// A match is 0xFF or 0. Count the bits into doubleword buckets.
	VPOPCNTD V0, V0
	VADDUDM	V0, V4, V4	// Accumulate the popcounts. They are 8x the count.
	VADDUDM	V2, V5, V5	// The count will be fixed up afterwards.
	ADD	$32, R3
	BDNZ	cmploop

	VADDUDM	V4, V5, V5
	MFVSRD	V5, R18
	VSLDOI	$8, V5, V5, V5
	MFVSRD	V5, R21
	ADD	R21, R18, R18
	ANDCC	$31, R4, R4

				inss = append(inss, ins2)
			}
		case AMOVHU, AMOVWU:
			if buildcfg.GORISCV64 >= 22 {
				// Use ZEXTH or ADDUW to extend.
				ins.as, ins.rs1, ins.rs2, ins.imm = AZEXTH, uint32(p.From.Reg), obj.REG_NONE, 0
				if p.As == AMOVWU {
					ins.as, ins.rs2 = AADDUW, REG_ZERO
				}
			} else {
				// Use SLLI/SRLI sequence to extend.