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Results 11 - 20 of 200 for if64 (0.13 sec)
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tensorflow/compiler/mlir/tensorflow/tests/lower_tf.mlir
func.func @Reciprocal_complexf64(%arg0: tensor<*xcomplex<f64>>) -> tensor<*xcomplex<f64>> { // CHECK: %[[ONE:.*]] = "tf.Const"() <{value = dense<(1.000000e+00,0.000000e+00)> : tensor<complex<f64>>}> : () -> tensor<complex<f64>> // CHECK: "tf.Div"(%[[ONE]], %arg0) : (tensor<complex<f64>>, tensor<*xcomplex<f64>>) -> tensor<*xcomplex<f64>> %0 = "tf.Reciprocal"(%arg0) : (tensor<*xcomplex<f64>>) -> tensor<*xcomplex<f64>> func.return %0 : tensor<*xcomplex<f64>> }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Jan 05 18:35:42 UTC 2024 - 92K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/stablehlo/passes/bridge/convert_tf_quant_to_mhlo_int_test.cc
device = "", lhs_quantization_axis = -1 : i64, lhs_quantization_max_val = 127 : i64, lhs_quantization_min_val = -128 : i64, output_quantization_axis = -1 : i64, output_quantization_max_val = 2147483647 : i64, output_quantization_min_val = -2147483648 : i64, rhs_quantization_axis = -1 : i64, rhs_quantization_max_val = 127 : i64, rhs_quantization_min_val = -128 : i64 } : (
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Apr 03 01:03:21 UTC 2024 - 35.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/lift_tflite_flex_ops.mlir
// CHECK-SAME: <{metadata = "", output_shapes = [#tf_type.shape<>], output_types = [!tf_type.string], predicate = @{{.*}}}> {Targuments = [!tf_type.resource, !tf_type.resource, i64, !tf_type.resource, !tf_type.resource, !tf_type.resource, !tf_type.resource, i64]} } // CHECK-LABEL: FailureOnInvalidOp func.func @FailureOnInvalidOp(%arg0: tensor<4xf64>, %arg1: tensor<4xf64>) -> tensor<4xf64> {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 6.1K bytes - Viewed (0) -
src/encoding/xml/read_test.go
<I32> 266703 </I32> <I32Neg> -266703 </I32Neg> <I64> 266703 </I64> <I64Neg> -266703 </I64Neg> <UI> 266703 </UI> <UI8> 112 </UI8> <UI16> 6703 </UI16> <UI32> 266703 </UI32> <UI64> 266703 </UI64> <F32> 266.703 </F32> <F32Neg> -266.703 </F32Neg> <F64> 266.703 </F64> <F64Neg> -266.703 </F64Neg> </WhitespaceValuesParent> `
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 26 19:58:28 UTC 2024 - 29.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/legalize-tf.mlir
func.return %0 : tensor<1x1x5x6x7xf32> // CHECK-LABEL: strided_slice_big_dims
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 05 01:54:33 UTC 2024 - 153.4K bytes - Viewed (0) -
platforms/native/platform-native/src/main/java/org/gradle/nativeplatform/toolchain/internal/msvcpp/VisualCppInstall.java
// TODO:ADAM - ARM only if the target OS is Windows 8 or later // TODO:MPUT - ARM also if the target OS is Windows RT or Windows Phone/Mobile/CE // TODO:ADAM - IA64 only if the target OS is Windows 2008 or earlier if (!targetPlatform.getOperatingSystem().isWindows()) { return null; } return platforms.get(getPlatformArchitecture(targetPlatform)); }
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Thu Nov 16 20:20:03 UTC 2023 - 2.3K bytes - Viewed (0) -
platforms/jvm/platform-jvm/src/main/java/org/gradle/platform/Architecture.java
/** * 32-bit complex instruction set computer (CISC) architectures, including "x32", "i386", "x86".. */ X86, /** * 64-bit variant of the X86 instruction set, including "x64", "x86_64", "amd64", "ia64". */ X86_64, /** * 64-bit reduced instruction set computer (RISC) architectures, including "aarch64", "arm64". */ AARCH64
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Thu Sep 28 15:09:49 UTC 2023 - 1.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/utils/convert_type.cc
if (type.isF16()) { *dtype = DT_HALF; return absl::OkStatus(); } else if (type.isF32()) { *dtype = DT_FLOAT; return absl::OkStatus(); } else if (type.isF64()) { *dtype = DT_DOUBLE; return absl::OkStatus(); } else if (type.isBF16()) { *dtype = DT_BFLOAT16; return absl::OkStatus(); } else if (type.isFloat8E4M3FN()) { *dtype = DT_FLOAT8_E4M3FN;
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Apr 26 09:37:10 UTC 2024 - 7.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/rewrite_util.h
if (complex_element_ty.isF32()) { return DenseElementsAttr::get( scalar_ty, static_cast<std::complex<float>>(raw_value)); } else if (complex_element_ty.isF64()) { return DenseElementsAttr::get( scalar_ty, static_cast<std::complex<double>>(raw_value)); } } llvm_unreachable("unsupported type"); }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 22 19:47:48 UTC 2024 - 4K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/utils/convert_type.cc
} else if (type.isF64()) { return tflite::TensorType_FLOAT64; } else if (mlir::isa<mlir::TF::StringType>(type)) { return tflite::TensorType_STRING; } else if (auto complex_type = mlir::dyn_cast<mlir::ComplexType>(type)) { if (complex_type.getElementType().isF32()) { return tflite::TensorType_COMPLEX64; } else if (complex_type.getElementType().isF64()) { return tflite::TensorType_COMPLEX128;
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue May 07 23:04:40 UTC 2024 - 8.2K bytes - Viewed (0)