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Results 11 - 20 of 20 for ORR (0.04 sec)

  1. test/codegen/math.go

    	// wasm:"F64Copysign"
    	sink64[0] = math.Copysign(a, b)
    
    	// amd64:"BTSQ\t[$]63"
    	// s390x:"LNDFR\t",-"MOVD\t"     (no integer load/store)
    	// ppc64x:"FCPSGN"
    	// riscv64:"FSGNJD"
    	// arm64:"ORR", -"AND"
    	sink64[1] = math.Copysign(c, -1)
    
    	// Like math.Copysign(c, -1), but with integer operations. Useful
    	// for platforms that have a copysign opcode to see if it's detected.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 6.2K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64.s

    	AND	$(1<<63-1), R1                      // AND	$9223372036854775807, R1        // 21f84092
    	ORR	$(1<<63), R1                        // ORR	$-9223372036854775808, R1       // 210041b2
    	ORR	$(1<<63-1), R1                      // ORR	$9223372036854775807, R1        // 21f840b2
    	EOR	$(1<<63), R1                        // EOR	$-9223372036854775808, R1       // 210041d2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
  3. test/codegen/rotate.go

    	i++
    }
    
    // combined arithmetic and rotate on arm64
    func checkArithmeticWithRotate(a *[1000]uint64) {
    	// arm64: "AND\tR[0-9]+@>51, R[0-9]+, R[0-9]+"
    	a[2] = a[1] & bits.RotateLeft64(a[0], 13)
    	// arm64: "ORR\tR[0-9]+@>51, R[0-9]+, R[0-9]+"
    	a[5] = a[4] | bits.RotateLeft64(a[3], 13)
    	// arm64: "EOR\tR[0-9]+@>51, R[0-9]+, R[0-9]+"
    	a[8] = a[7] ^ bits.RotateLeft64(a[6], 13)
    	// arm64: "MVN\tR[0-9]+@>51, R[0-9]+"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 6K bytes
    - Viewed (0)
  4. test/codegen/bits.go

    	a[1] = ^(y ^ z)
    
    	// arm64:`EON\t`,-`XOR`
    	a[2] = x ^ ^z
    
    	// arm64:`EON\t`,-`EOR`,-`MVN`
    	return n ^ (m ^ 0xffffffffffffffff)
    }
    
    func op_orn(x, y uint32) uint32 {
    	// arm64:`ORN\t`,-`ORR`
    	return x | ^y
    }
    
    // check bitsets
    func bitSetPowerOf2Test(x int) bool {
    	// amd64:"BTL\t[$]3"
    	return x&8 == 8
    }
    
    func bitSetTest(x int) bool {
    	// amd64:"ANDL\t[$]9, AX"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 7.8K bytes
    - Viewed (0)
  5. src/crypto/md5/md5block_arm.s

    	ROUND3(Rb, Rc, Rd, Ra,  2, 23, Rc3)
    
    // a += (c^(b|^d)) + X[index] + const
    // a = a<<shift | a>>(32-shift) + b
    #define ROUND4(Ra, Rb, Rc, Rd, index, shift, Rconst) \
    	MVN	Rd, Rt0			; \
    	ORR	Rb, Rt0			; \
    	EOR	Rc, Rt0			; \
    	MOVW	(index<<2)(Rdata), Rt1	; \
    	ADD	Rt1, Rt0			; \
    	ADD	Rconst, Rt0			; \
    	ADD	Rt0, Ra			; \
    	ADD	Ra@>(32-shift), Rb, Ra	;
    
    	MOVM.IA.W (Rtable), [Rc0,Rc1,Rc2,Rc3]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 8.8K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	ORNW R4@>11, R16, R3                       // 032ee42a
    	ORN R22@>19, R3, R3                        // 634cf6aa
    	ORRW $4294443071, R15, R24                 // f8490d32
    	ORR $-3458764513820540929, R12, R22        // 96f542b2
    	ORRW R13<<4, R8, R26                       // 1a110d2a
    	ORR R3<<22, R5, R6                         // a65803aa
    	PRFM (R8), $25                             // 190180f9
    	PRFM (R2), PLDL1KEEP                       // 400080f9
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  7. src/crypto/tls/testdata/Client-TLSv12-RenegotiateOnce

    00000330  c3 fb 96 05 bf b5 bd bf  e2 28 07 7e 51 a6 84 90  |.........(.~Q...|
    00000340  bf 9e 2e f6 b5 04 8e 06  7a 63 c8 00 84 a1 a3 2c  |........zc.....,|
    00000350  f3 6f 52 52 c4 ce 4a 59  31 1f d4 ab 2e f4 75 90  |.oRR..JY1.....u.|
    00000360  a5 3b ff ab 20 be 51 92  c5 f4 4d 8b f2 2a a7 ff  |.;.. .Q...M..*..|
    00000370  90 07 40 3e d6 9c cf 23  54 d1 65 d3 74 79 af 51  |..@>...#T.e.ty.Q|
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 22:33:38 UTC 2024
    - 18.4K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/parse.go

    	case lex.LSH:
    		op = 0
    	case lex.RSH:
    		op = 1
    	case lex.ARR:
    		op = 2
    	case lex.ROT:
    		// following instructions on ARM64 support rotate right
    		// AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN
    		op = 3
    	}
    	tok := p.next()
    	str := tok.String()
    	var count int16
    	switch tok.ScanToken {
    	case scanner.Ident:
    		if p.arch.Family == sys.ARM64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Feb 21 14:34:57 UTC 2024
    - 36.9K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/arm/asm5.go

    		rt := int(p.To.Reg)
    		if r == 0 {
    			r = rt
    		}
    		x, y := immrot2a(uint32(c.instoffset))
    		var as2 obj.As
    		switch p.As {
    		case AADD, ASUB, AORR, AEOR, ABIC:
    			as2 = p.As // ADD, SUB, ORR, EOR, BIC
    		case ARSB:
    			as2 = AADD // RSB -> RSB/ADD pair
    		case AADC:
    			as2 = AADD // ADC -> ADC/ADD pair
    		case ASBC:
    			as2 = ASUB // SBC -> SBC/SUB pair
    		case ARSC:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 79.4K bytes
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  10. src/cmd/internal/obj/arm64/asm7.go

    			o1 |= 1 << 10
    		} else {
    			o1 |= 3 << 10
    		}
    		o1 |= ((uint32(v) & 0x1FF) << 12) | (uint32(p.To.Reg&31) << 5) | uint32(p.From.Reg&31)
    
    	case 24: /* mov/mvn Rs,Rd -> add $0,Rs,Rd or orr Rs,ZR,Rd */
    		rf := int(p.From.Reg)
    		rt := int(p.To.Reg)
    		if rf == REGSP || rt == REGSP {
    			if p.As == AMVN || p.As == AMVNW {
    				c.ctxt.Diag("illegal SP reference\n%v", p)
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
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