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Results 11 - 17 of 17 for andc (0.13 sec)

  1. src/runtime/mbitmap.go

    // by checking typ.PtrBytes.
    //
    // The typ argument is the type of the space at src and dst (and the
    // element type if src and dst refer to arrays) and it is optional.
    // If typ is nil, the barrier will still behave as expected and typ
    // is used purely as an optimization. However, it must be used with
    // care.
    //
    // If typ is not nil, then src and dst must point to one or more values
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 00:18:55 UTC 2024
    - 60K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewrite.go

    	return (v&vp == 0 || vn&vpn == 0) && v != 0
    }
    
    // Compress mask and shift into single value of the form
    // me | mb<<8 | rotate<<16 | nbits<<24 where me and mb can
    // be used to regenerate the input mask.
    func encodePPC64RotateMask(rotate, mask, nbits int64) int64 {
    	var mb, me, mbn, men int
    
    	// Determine boundaries and then decode them
    	if mask == 0 || ^mask == 0 || rotate >= nbits {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 64.2K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/loong64/asm.go

    				otxt := p.To.Target().Pc - pc
    
    				// On loong64, the immediate value field of the conditional branch instructions
    				// BFPT and BFPT is 21 bits, and the others are 16 bits. The jump target address
    				// is to logically shift the immediate value in the instruction code to the left
    				// by 2 bits and then sign extend.
    				bound := int64(1 << (18 - 1))
    
    				switch p.As {
    				case ABFPT, ABFPF:
    					bound = int64(1 << (23 - 1))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 61.8K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/riscv/obj.go

    	}
    }
    
    // preprocess generates prologue and epilogue code, computes PC-relative branch
    // and jump offsets, and resolves pseudo-registers.
    //
    // preprocess is called once per linker symbol.
    //
    // When preprocess finishes, all instructions in the symbol are either
    // concrete, real RISC-V instructions or directive pseudo-ops like TEXT,
    // PCDATA, and FUNCDATA.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  5. guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java

    21,ohsdaerpsym,?r&euefknuf.neiw,o??v&g?irp,?xi2,ytic-amil,zib,?c?e!s??hc?l?mami?rcomed??b!.&gro?moc?ten?ude?vog??b?gl??c&atnoc?e&les?rid!txen????dimhcs?e!.&eman?gro?moc?ofni?ten?ude?vog?zib??b?em?grat?id?k&circ?ram??n!.&0rab,1rab,2rab,5inu,6vnyd,7&7ndc.r,erauqs,?a&l&-morf,moob,?minifed,remacytirucesym,tadsyawla,z,?b&boi,ewdarym,g,lyltsaf:.pam,,?c&i&nagro-gnitae,tats-oieboda,?paidemym,?d&e&calpb,ziamaka,?feruza,hiamaka,irgevissam.saap.&1-&gs,nol,rf,yn,?2-&nol,yn,??nab-eht-ni,uolc&meaeboda,nievas....
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Thu Mar 21 21:04:43 UTC 2024
    - 72.4K bytes
    - Viewed (0)
  6. android/guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java

    21,ohsdaerpsym,?r&euefknuf.neiw,o??v&g?irp,?xi2,ytic-amil,zib,?c?e!s??hc?l?mami?rcomed??b!.&gro?moc?ten?ude?vog??b?gl??c&atnoc?e&les?rid!txen????dimhcs?e!.&eman?gro?moc?ofni?ten?ude?vog?zib??b?em?grat?id?k&circ?ram??n!.&0rab,1rab,2rab,5inu,6vnyd,7&7ndc.r,erauqs,?a&l&-morf,moob,?minifed,remacytirucesym,tadsyawla,z,?b&boi,ewdarym,g,lyltsaf:.pam,,?c&i&nagro-gnitae,tats-oieboda,?paidemym,?d&e&calpb,ziamaka,?feruza,hiamaka,irgevissam.saap.&1-&gs,nol,rf,yn,?2-&nol,yn,??nab-eht-ni,uolc&meaeboda,nievas....
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Thu Mar 21 21:04:43 UTC 2024
    - 72.4K bytes
    - Viewed (1)
  7. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (ADD x (SRA y z)) => (ADDshiftRAreg x y z)
    (ADC x (SLLconst [c] y) flags) => (ADCshiftLL x y [c] flags)
    (ADC x (SRLconst [c] y) flags) => (ADCshiftRL x y [c] flags)
    (ADC x (SRAconst [c] y) flags) => (ADCshiftRA x y [c] flags)
    (ADC x (SLL y z) flags) => (ADCshiftLLreg x y z flags)
    (ADC x (SRL y z) flags) => (ADCshiftRLreg x y z flags)
    (ADC x (SRA y z) flags) => (ADCshiftRAreg x y z flags)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
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