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Results 11 - 20 of 24 for NEG (0.63 sec)

  1. src/time/time.go

    // returns the offset of the first character.
    func (d Duration) format(buf *[32]byte) int {
    	// Largest time is 2540400h10m10.000000000s
    	w := len(buf)
    
    	u := uint64(d)
    	neg := d < 0
    	if neg {
    		u = -u
    	}
    
    	if u < uint64(Second) {
    		// Special case: if duration is smaller than a second,
    		// use smaller units, like 1.2ms
    		var prec int
    		w--
    		buf[w] = 's'
    		w--
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 29 17:58:53 UTC 2024
    - 50.7K bytes
    - Viewed (0)
  2. src/math/big/int_test.go

    		nil,
    		{0},
    		{1},
    		{0, 1, 2, 3, 4},
    		{4, 3, 2, 1, 0},
    		{4, 3, 2, 1, 0, 0, 0, 0},
    	} {
    		var z Int
    		z.neg = true
    		got := z.SetBits(test)
    		want := norm(test)
    		if got.abs.cmp(want) != 0 {
    			t.Errorf("SetBits(%v) = %v; want %v", test, got.abs, want)
    		}
    
    		if got.neg {
    			t.Errorf("SetBits(%v): got negative result", test)
    		}
    
    		bits := nat(z.Bits())
    		if bits.cmp(want) != 0 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 18:42:28 UTC 2024
    - 58.5K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "NEGshiftLL", argLength: 1, reg: gp11, asm: "NEG", aux: "Int64"},                   // -(arg0<<auxInt), auxInt should be in the range 0 to 63.
    		{name: "NEGshiftRL", argLength: 1, reg: gp11, asm: "NEG", aux: "Int64"},                   // -(arg0>>auxInt), unsigned shift, auxInt should be in the range 0 to 63.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/lower_tf.mlir

      // CHECK-DAG: %[[LE2:.*]] = "tf.LessEqual"(%[[OFFSET]], %[[NUM_LOWER_OR_M]]) : (tensor<4x5xi64>, tensor<i64>) -> tensor<4x5xi1>
      // CHECK-DAG: %[[NEG:.*]] = "tf.Neg"(%[[NUM_UPPER_OR_N]]) : (tensor<i64>) -> tensor<i64>
      // CHECK-DAG: %[[GE:.*]] = "tf.GreaterEqual"(%[[OFFSET]], %[[NEG]]) : (tensor<4x5xi64>, tensor<i64>) -> tensor<4x5xi1>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Jan 05 18:35:42 UTC 2024
    - 92K bytes
    - Viewed (0)
  5. src/cmd/vendor/github.com/ianlancetaylor/demangle/demangle.go

    		}
    		st.subs.add(ret)
    	}
    	return ret
    }
    
    // number parses:
    //
    //	number ::= [n] <(non-negative decimal integer)>
    func (st *state) number() int {
    	neg := false
    	if len(st.str) > 0 && st.str[0] == 'n' {
    		neg = true
    		st.advance(1)
    	}
    	if len(st.str) == 0 || !isDigit(st.str[0]) {
    		st.fail("missing number")
    	}
    	val := 0
    	for len(st.str) > 0 && isDigit(st.str[0]) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 31 19:48:28 UTC 2024
    - 94.1K bytes
    - Viewed (0)
  6. guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java

    ,,oc?saak,t&en?ikcats,???i&a?v??k!.&gro?ku,lim?moc?oi,pj,su,ten?ude?v&og?t,???m!.&drp?gro?lim?m&o&c?n??t??oc?ude?vog??pk??n!.&dtl,eman?gro?hcs?i!bom??l&im?oc,?m&oc!.topsgolb,?rif,?neg,ogn,ten?ude?vog??aw?i!b!mulp??car?d&art?dew??h&sif?tolc??k&iv?oo&b?c???ls?n&aelc?iart??p!pohs??re&enigne?tac??t&ad?ekram?hgil?lusnoc?neg?ov?soh!.tfarcnepo,??vi&g?l???o!s??u&rehcisrev?smas?tarebsnegömrev???o&d?lb?og!.&duolc,etalsnart,???r&2n084qlj--nx?ebmoolb?o!.&77ndc.c:sr,,a&remacytirucesym,t&neimip,sivretla,?z,?b...
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Thu Mar 21 21:04:43 UTC 2024
    - 72.4K bytes
    - Viewed (0)
  7. android/guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java

    ,,oc?saak,t&en?ikcats,???i&a?v??k!.&gro?ku,lim?moc?oi,pj,su,ten?ude?v&og?t,???m!.&drp?gro?lim?m&o&c?n??t??oc?ude?vog??pk??n!.&dtl,eman?gro?hcs?i!bom??l&im?oc,?m&oc!.topsgolb,?rif,?neg,ogn,ten?ude?vog??aw?i!b!mulp??car?d&art?dew??h&sif?tolc??k&iv?oo&b?c???ls?n&aelc?iart??p!pohs??re&enigne?tac??t&ad?ekram?hgil?lusnoc?neg?ov?soh!.tfarcnepo,??vi&g?l???o!s??u&rehcisrev?smas?tarebsnegömrev???o&d?lb?og!.&duolc,etalsnart,???r&2n084qlj--nx?ebmoolb?o!.&77ndc.c:sr,,a&remacytirucesym,t&neimip,sivretla,?z,?b...
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Thu Mar 21 21:04:43 UTC 2024
    - 72.4K bytes
    - Viewed (1)
  8. src/cmd/compile/internal/ssa/_gen/S390XOps.go

    		{name: "RISBGZ", argLength: 1, reg: gp11, asm: "RISBGZ", aux: "S390XRotateParams", clobberFlags: true},                   // rotate then insert selected bits [into zero]
    
    		// unary ops
    		{name: "NEG", argLength: 1, reg: gp11, asm: "NEG", clobberFlags: true},   // -arg0
    		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW", clobberFlags: true}, // -arg0
    
    		{name: "NOT", argLength: 1, reg: gp11, resultInArg0: true, clobberFlags: true},  // ^arg0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 52.5K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/riscv/obj.go

    		// Rotation instructions are supported natively.
    		return []*instruction{ins}
    	}
    
    	switch ins.as {
    	case AROL, AROLW, AROR, ARORW:
    		// ROL -> OR (SLL x y) (SRL x (NEG y))
    		// ROR -> OR (SRL x y) (SLL x (NEG y))
    		sllOp, srlOp := ASLL, ASRL
    		if ins.as == AROLW || ins.as == ARORW {
    			sllOp, srlOp = ASLLW, ASRLW
    		}
    		shift1, shift2 := sllOp, srlOp
    		if ins.as == AROR || ins.as == ARORW {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (Avg32u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y)
    
    (And(32|16|8) ...) => (AND ...)
    (Or(32|16|8) ...) => (OR ...)
    (Xor(32|16|8) ...) => (XOR ...)
    
    // unary ops
    (Neg(32|16|8) x) => (RSBconst [0] x)
    (Neg(32|64)F ...) => (NEG(F|D) ...)
    
    (Com(32|16|8) ...) => (MVN ...)
    
    (Sqrt ...) => (SQRTD ...)
    (Sqrt32 ...) => (SQRTF ...)
    (Abs ...) => (ABSD ...)
    
    // TODO: optimize this for ARMv5 and ARMv6
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
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