Search Options

Results per page
Sort
Preferred Languages
Advance

Results 21 - 26 of 26 for addPod (0.12 sec)

  1. tensorflow/compiler/mlir/lite/transforms/optimize_patterns.td

      "llvm::all_of($0.getUsers(), [&](Operation *user) {"
      "  if(!llvm::isa<TFL::AddOp>(user)) return false;"
      "  if(!user->getOperand(0).getDefiningOp<"#op_to_fuse_with#">()) return false;"
      "  return true;"
      "})">, "all users are AddOp and can fuse with "#op_to_fuse_with#"">;
    
    // TODO(b/294385379): This pattern only appears when we convert
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 16 20:31:41 UTC 2024
    - 66.4K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/S390XOps.go

    //        using the SB 'register' to address data. This is because many machine
    //        instructions do not have relative long (RL suffix) equivalents. For example,
    //        ADDload, which is assembled as AG.
    //
    //     2. Loads and stores using relative addressing require the data be aligned
    //        according to its size (8-bytes for double words, 4-bytes for words
    //        and so on).
    //
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 52.5K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/mips/asm0.go

    					q = c.newprog()
    					q.Link = p.Link
    					p.Link = q
    					q.As = AJMP
    					q.Pos = p.Pos
    					q.To.Type = obj.TYPE_BRANCH
    					q.To.SetTarget(q.Link.Link)
    
    					c.addnop(p.Link)
    					c.addnop(p)
    					bflag = 1
    				}
    			}
    
    			m = int(o.size)
    			if m == 0 {
    				if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
    					c.ctxt.Diag("zero-width instruction\n%v", p)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 17:46:09 UTC 2024
    - 53.6K bytes
    - Viewed (0)
  4. tensorflow/compiler/jit/mark_for_compilation_pass_test.cc

          NodeDefBuilder builder(name, "NoOp");
          NodeDef def;
          TF_CHECK_OK(builder.Finalize(&def));
    
          Status status;
          Node* node = graph->AddNode(def, &status);
          TF_CHECK_OK(status);
          return node;
        };
    
        Node* a = BuildNoopNode("a", graph.get());
        Node* b = BuildNoopNode("b", graph.get());
        Node* c = BuildNoopNode("c", graph.get());
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Feb 14 10:11:10 UTC 2024
    - 79.6K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true},
    		{name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true},
    
    		// 3-operand, the addend comes first
    		{name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS"},   // +arg0 + (arg1 * arg2)
    		{name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD"},   // +arg0 + (arg1 * arg2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (NMULD (NEGD x) y) => (MULD x y)
    
    // the result will overwrite the addend, since they are in the same register
    (ADDF a (MULF x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULAF a x y)
    (ADDF a (NMULF x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULSF a x y)
    (ADDD a (MULD x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULAD a x y)
    (ADDD a (NMULD x y)) && a.Uses == 1 && buildcfg.GOARM.Version >= 6 => (MULSD a x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
Back to top