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Results 11 - 16 of 16 for vsrad (0.03 sec)

  1. src/cmd/internal/obj/ppc64/doc.go

    Go compiler will add appropriate code to compare the shift value to achieve the
    correct result, and the assembler does not add extra checking.
    
    Examples:
    
    	SRAD $8,R3,R4		=>	sradi r4,r3,8
    	SRD $8,R3,R4		=>	rldicl r4,r3,56,8
    	SLD $8,R3,R4		=>	rldicr r4,r3,8,55
    	SRAW $16,R4,R5		=>	srawi r5,r4,16
    	SRW $40,R4,R5		=>	rlwinm r5,r4,0,0,31
    	SLW $12,R4,R5		=>	rlwinm r5,r4,12,0,19
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 16:47:45 UTC 2023
    - 11.3K bytes
    - Viewed (0)
  2. src/math/erfc_s390x.s

    TEXT	·erfcAsm(SB), NOSPLIT|NOFRAME, $0-16
    	MOVD	x+0(FP), R1
    	MOVD	$Neg2p11, R2
    	CMPUBGT	R1, R2, usego
    
    	FMOVD	x+0(FP), F0
    	MOVD	$·erfcrodataL38<>+0(SB), R9
    	FMOVD	F0, F2
    	SRAD	$48, R1
    	MOVH	R1, R2
    	ANDW	$0x7FFF, R1
    	MOVH	$Pos15, R3
    	CMPW	R1, R3
    	BGT	usego
    	MOVH	$0x3FFF, R3
    	MOVW	R1, R6
    	MOVW	R3, R7
    	CMPBGT	R6, R7, L2
    	MOVH	$0x3FEF, R3
    	MOVW	R3, R7
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 14.4K bytes
    - Viewed (0)
  3. src/math/pow_s390x.s

    	WFMADB	V3, V1, V5, V1
    	MOVD	$·powtexp<>+0(SB), R3
    	WORD	$0x68343000	//ld	%f3,0(%r4,%r3)
    	FMADD	F3, F4, F4
    	RISBGN	$0, $15, $48, R2, R5
    	WFMADB	V4, V1, V3, V4
    	LGDR	F6, R2
    	LDGR	R5, F1
    	SRAD	$48, R2, R2
    	FMADD	F1, F4, F1
    	RLL	$16, R2, R2
    	ANDW	$0x7FFF0000, R2
    	WORD	$0xC22B3F71	//alfi	%r2,1064370176
    	BYTE	$0x00
    	BYTE	$0x00
    	ORW	R2, R1, R3
    	MOVW	R3, R6
    	CMPBLT	R6, $0, L43
    L1:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 16.3K bytes
    - Viewed (0)
  4. src/math/big/arith_ppc64x.s

    	ADD     $-2, R4, R16
    	PCALIGN $16
    loopback:
    	ADD     $-1, R8, R10
    	SLD     $3, R10
    	LXVD2X  (R6)(R10), VS32 // load x[i-1], x[i]
    	SLD     $3, R8, R12
    	LXVD2X  (R6)(R12), VS33 // load x[i], x[i+1]
    
    	VSRD    V0, V4, V3      // x[i-1]>>s, x[i]>>s
    	VSLD    V1, V2, V5      // x[i]<<ŝ, x[i+1]<<ŝ
    	VOR     V3, V5, V5      // Or(|) the two registers together
    	STXVD2X VS37, (R3)(R10) // store into z[i-1] and z[i]
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 18:17:17 UTC 2024
    - 16.8K bytes
    - Viewed (0)
  5. src/crypto/aes/gcm_ppc64x.s

    	VADDUBM  XC2, XC2, XC2       // 0xc2...
    	VSPLTISB $7, T2
    	VOR      XC2, T1, XC2        // 0xc2....01
    	VSPLTB   $0, H, T1           // most significant byte
    	VSL      H, T0, H            // H<<=1
    	VSRAB    T1, T2, T1          // broadcast carry bit
    	VAND     T1, XC2, T1
    	VXOR     H, T1, IN           // twisted H
    
    	VSLDOI $8, IN, IN, H      // twist even more ...
    	VSLDOI $8, ZERO, XC2, XC2 // 0xc2.0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 27.1K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/ppc64/asm9_gtables.go

    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 16 20:18:50 UTC 2022
    - 42.6K bytes
    - Viewed (0)
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