MOVM.IB	[R0-R4], (F1)      // ERROR "illegal base register"
	MOVM.DB	[R0-R4], (F1)      // ERROR "illegal base register"
	MOVW	R0<<0(F1), R1      // ERROR "illegal base register"
	MOVB	R0<<0(F1), R1      // ERROR "illegal base register"
	MOVW	R1, R0<<0(F1)      // ERROR "illegal base register"
	MOVB	R2, R0<<0(F1)      // ERROR "illegal base register"
	MOVF	0x00ffffff(F2), F1 // ERROR "illegal base register"

				// both 1st operand and 3rd operand are (Rs, Rs+1) register pair.
				// And the register pair must be contiguous.
				if (a[0].Type != obj.TYPE_REGREG) || (a[2].Type != obj.TYPE_REGREG) {
					p.errorf("invalid addressing modes for 1st or 3rd operand to %s instruction, must be register pair", op)
					return
				}
				// For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can

	// Override the default Deflate compressor with a higher compression level.

	// Create a buffer to write our archive to.
	buf := new(bytes.Buffer)

	// Create a new zip archive.
	w := zip.NewWriter(buf)

	// Register a custom Deflate compressor.
	w.RegisterCompressor(zip.Deflate, func(out io.Writer) (io.WriteCloser, error) {
		return flate.NewWriter(out, flate.BestCompression)
	})

	// Proceed to add files to w.

	BuildComment                          // //go:build or +build comment
	macroName                             // name of macro that should not be expanded
)

// IsRegisterShift reports whether the token is one of the ARM register shift operators.
func IsRegisterShift(r ScanToken) bool {
	return ROT <= r && r <= LSH // Order looks backwards because these are negative.
}

func (t ScanToken) String() string {
	switch t {
	case scanner.EOF: