FPSCR

	SP = R13
	LR = R14
	PC = R15
)

func (Reg) IsArg() {}

func (r Reg) String() string {
	switch r {
	case APSR:
		return "APSR"
	case APSR_nzcv:
		return "APSR_nzcv"
	case FPSCR:
		return "FPSCR"
	case SP:
		return "SP"
	case PC:
		return "PC"
	case LR:
		return "LR"
	}
	if R0 <= r && r <= R15 {
		return fmt.Sprintf("R%d", int(r-R0))
	}

func PtraceSetRegs386(pid int, regs *PtraceRegs386) error {
	return ptracePtr(PTRACE_SETREGS, pid, 0, unsafe.Pointer(regs))
}

// PtraceRegsAmd64 is the registers used by amd64 binaries.
type PtraceRegsAmd64 struct {
	R15      uint64
	R14      uint64
	R13      uint64
	R12      uint64
	Rbp      uint64
	Rbx      uint64
	R11      uint64
	R10      uint64
	R9       uint64
	R8       uint64
	Rax      uint64
	Rcx      uint64

	FMOVD   x+0(FP), F0
	MOVD    $log10rodataL19<>+0(SB), R9
	FMOVD   F0, x-8(SP)
	WORD    $0xC0298006     //iilf %r2,2147909631
	BYTE    $0x7F
	BYTE    $0xFF
	WORD    $0x5840F008     //l %r4, 8(%r15)
	SUBW    R4, R2, R3
	RISBGZ	$32, $47, $0, R3, R5
	MOVH    $0x0, R1
	RISBGN	$0, $31, $32, R5, R1
	WORD    $0xC0590016     //iilf %r5,1507327
	BYTE    $0xFF
	BYTE    $0xFF
	MOVW    R4, R10
	MOVW    R5, R11

	*R10
	*R11
	*R12
}

type R6 R5
type R7 R5
type R8 R5

type R9 struct {
	*R13
	*R14
	*R15
	*R16
}

type R10 R9
type R11 R9
type R12 R9

type R13 struct {
	*R17
	*R18
	*R19
	*R20
}

type R14 R13
type R15 R13
type R16 R13

type R17 struct {
	*R21
	*R22
	*R23
	*R24
}

type R18 R17
type R19 R17

 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

package org.gradle.integtests.tooling.r15


import org.gradle.integtests.tooling.fixture.ToolingApiSpecification
import org.gradle.tooling.model.GradleProject

class ToolingApiConfigurationOnDemandCrossVersionSpec extends ToolingApiSpecification {

	MOVW	R0, 12(R4)		// save return value to libcall->r1
	MOVW	R1, 16(R4)

	// GetLastError
	MRC	15, 0, R1, C13, C0, 2
	MOVW	0x34(R1), R0
	MOVW	R0, 20(R4)		// store in libcall->err

	MOVM.IA.W (R13), [R4, R5, R15]

TEXT runtime·getlasterror(SB),NOSPLIT,$0
	MRC	15, 0, R0, C13, C0, 2
	MOVW	0x34(R0), R0
	MOVW	R0, ret+0(FP)
	RET

// Called by Windows as a Vectored Exception Handler (VEH).

	print("r10  ", hex(c.r10()), "\t")
	print("r11  ", hex(c.r11()), "\n")
	print("r12  ", hex(c.r12()), "\t")
	print("r13  ", hex(c.r13()), "\n")
	print("r14  ", hex(c.r14()), "\t")
	print("r15  ", hex(c.r15()), "\n")
	print("r16  ", hex(c.r16()), "\t")
	print("r17  ", hex(c.r17()), "\n")
	print("r18  ", hex(c.r18()), "\t")
	print("r19  ", hex(c.r19()), "\n")
	print("r20  ", hex(c.r20()), "\t")

	print("r10     ", hex(c.r10()), "\n")
	print("r11     ", hex(c.r11()), "\n")
	print("r12     ", hex(c.r12()), "\n")
	print("r13     ", hex(c.r13()), "\n")
	print("r14     ", hex(c.r14()), "\n")
	print("r15     ", hex(c.r15()), "\n")
	print("r16     ", hex(c.r16()), "\n")
	print("r17     ", hex(c.r17()), "\n")
	print("r18     ", hex(c.r18()), "\n")
	print("r19     ", hex(c.r19()), "\n")
	print("r20     ", hex(c.r20()), "\n")

1. Most instructions use width suffixes of instruction names to indicate operand width rather than
using different register names.

Examples:

	ADC R24, R14, R12          <=>     adc x12, x14, x24
	ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
	FCMPS F2, F3               <=>     fcmp s3, s2
	FCMPD F2, F3               <=>     fcmp d3, d2
	FCVTDH F2, F3              <=>     fcvt h3, d2

		ctxt.Diag("don't know how to handle %v with -dynlink", p)
	}
	var source *obj.Addr
	// MOVx sym, Ry becomes $MOV sym@GOT, R15; MOVx (R15), Ry
	// MOVx Ry, sym becomes $MOV sym@GOT, R15; MOVx Ry, (R15)
	// An addition may be inserted between the two MOVs if there is an offset.
	if p.From.Name == obj.NAME_EXTERN && !p.From.Sym.Local() {