const int64_t output_size = (lhs_size_dilated + stride - 1) / stride;
      const int64_t total_padding = std::max(
          (output_size - 1) * stride + rhs_size_dilated - lhs_size_dilated,
          static_cast<int64_t>(0));
      const int64_t padding_begin = total_padding / 2;
      const int64_t padding_end = total_padding - padding_begin;

}

}  // namespace

template <typename BatchMatMulOpType>
TF::ReshapeOp ConvertTFBatchMatMulOp<BatchMatMulOpType>::createReshapeOp(
    Value value, ArrayRef<int64_t> shape, Type element_type, Location loc,
    PatternRewriter& rewriter) {
  int64_t shape_rank = shape.size();
  auto shape_spec_type =
      RankedTensorType::get({shape_rank}, rewriter.getIntegerType(64));
  Type resultType = RankedTensorType::get(shape, element_type);

    llvm::function_ref<std::optional<Type>(int64_t)> arg_to_stack_type,
    llvm::function_ref<void(ArrayRef<BlockArgument>)> handle_new_size_vars =
        nullptr) {
  auto new_input_types = llvm::to_vector<8>(func.getFunctionType().getInputs());
  auto size_var_type = GetSizeVarType(OpBuilder(func));
  int64_t original_arg_count = new_input_types.size();
  for (int64_t i = 0; i < original_arg_count; ++i) {

// permutation of `kNchwToNhwcPermutation`.
inline constexpr std::array<int64_t, 4> kNhwcToNchwPermutation = {0, 3, 1, 2};

// Permutation from the NCHW tensor format to NHWC. This is an inverse
// permutation of `kNchwToNhwcPermutation`.
inline constexpr std::array<int64_t, 4> kNchwToNhwcPermutation = {0, 2, 3, 1};

// Permutation from the OIHW (== (output features, input features, height,

}

void TF_ShapeInferenceContextDim(TF_ShapeInferenceContext* ctx,
                                 TF_ShapeHandle* shape_handle, int64_t i,
                                 TF_DimensionHandle* result) {
  int64_t rank = TF_ShapeInferenceContextRank(ctx, shape_handle);
  auto* cc_result = reinterpret_cast<DimensionHandle*>(result);

  if (i < -rank || i >= rank) {
    *cc_result = DimensionHandle();
    return;
  }

TEST(PermutationTest, PermuteEmptyArray) {
  const SmallVector<int> permutation_result =
      Permute<int>(SmallVector<int>{}, SmallVector<int64_t>{});
  EXPECT_THAT(permutation_result, IsEmpty());
}

TEST(PermutationTest, PermuteOneElement) {
  const SmallVector<int> single_element_array = {8};
  const SmallVector<int64_t> permutation = {0};

  const SmallVector<int> permutation_result =
      Permute<int>(single_element_array, permutation);

  // a TFRT backed tensor.
  // TODO(bmzhao): Add benchmarks on overhead for this function; we can
  // consider using int64_t* + length rather than vector.
  static Tensor FromBuffer(TF_DataType dtype, const std::vector<int64_t>& shape,
                           void* data, size_t len, DeleterCallback deleter,
                           Status* status);

                              .HostMemory("output")                            \
                              .TypeConstraint<int64_t>("out_type")             \
                              .TypeConstraint("T", TYPES),                     \
                          ShapeOp<int64_t>);                                   \
  REGISTER_KERNEL_BUILDER(Name("ShapeN")                                       \

      std::iota(minor_to_major.begin(), minor_to_major.end(), 0);
      std::sort(minor_to_major.begin(), minor_to_major.end(),
                [=](int64_t a, int64_t b) {
                  int64_t da = t.getDimSize(a);
                  int64_t db = t.getDimSize(b);
                  return da > db || (da == db && a > b);
                });
    }
    std::vector<Attribute> elements;

std::optional<RankedTensorType> InferXlaConvOutputShape(
    llvm::SmallVector<int64_t> input_tensor_dims,
    llvm::SmallVector<int64_t> kernel_tensor_dims,
    llvm::SmallVector<int64_t> window_strides,
    llvm::SmallVector<std::pair<int64_t, int64_t>> paddings,
    llvm::SmallVector<int64_t> lhs_dilations,
    llvm::SmallVector<int64_t> rhs_dilations, int64_t batch_group_count,
    xla::ConvolutionDimensionNumbers dnums, Type element_type) {